View PIC16F87-ISO_5296472.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2003 microchip technology inc. preliminary ds30487b pic16f87/88 data sheet 18/20/28-pin enhanced flash microcontrollers with nanowatt technology
ds30487b-page ii preliminary ? 2003 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of mi crochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. accuron, application maestro, dspicdem, dspicdem.net, economonitor, fansense, flexrom, fuzzylab, in- circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, picc, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smar ttel and total endurance are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned he rein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are comm itted to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
? 2003 microchip technology inc. preliminary ds30487b-page 1 pic16f87/88 low-power features: power managed modes: - primary run: rc oscillator, 76 a, 1 mhz, 2v - rc_run: 7 a, 31.25 khz, 2v - sec_run: 9 a, 32 khz, 2v - sleep: 0.1 a, 2v timer1 oscillator: 1.8 a, 32 khz, 2v watchdog timer: 2.2 a, 2v two-speed oscillator start-up oscillators: three crystal modes: - lp, xt, hs: up to 20 mhz two external rc modes one external clock mode: - ecio: up to 20 mhz internal oscillator block: - 8 user selectable frequencies: 31 khz, 125 khz, 250 khz, 500 khz, 1 mhz, 2 mhz, 4mhz, 8mhz peripheral features: capture, compare, pwm (ccp) module: - capture is 16-bit, max. resolution is 12.5 ns - compare is 16-bit, max. resolution is 200 ns - pwm max. resolution is 10-bit 10-bit, 7-channel analog-to-digital converter synchronous serial port (ssp) with spi? (master/slave) and i 2 c? (slave) addressable universal synchronous asynchronous receiver transmitter (usart/sci) with 9-bit address detection: - rs-232 operation using internal oscillator (no external crystal required) dual analog comparator module: - programmable on-chip voltage reference - programmable input multiplexing from device inputs and internal voltage reference - comparator outputs are externally accessible pin diagram special microcontroller features: 100,000 erase/write cycles enhanced flash program memory typical 1,000,000 typical erase/write cycles eeprom data memory typical eeprom data retention: > 40 years in-circuit serial programming? (icsp?) - via two pins processor read/write access to program memory low-voltage programming in-circuit debugging via two pins extended watchdog timer (wdt): - programmable period from 1 ms to 268s wide operating voltage range: 2.0v to 5.5v ra1/an1 ra0/an0 ra7/osc1/clki ra6/osc2/clko v dd rb7/an6/pgd/ rb6/an5/pgc/ rb5/ss /tx/ck rb4/sck/scl ra3/an3/v ref +/ ra4/an4/t0cki/ ra5/mclr /v pp v ss rb0/int/ccp1 (1) rb1/sdi/sda rb2/sdo/rx/dt rb3/pgm/ccp1 (1) 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pic16f88 t1osi t1oso/t1cki c2out c1out v ref - ra2/an2/cv ref / 18-pin dip, soic note 1: the ccp1 pin is determined by ccpmx in configuration word 1 register. device program memory data memory i/o pins 10-bit a/d (ch) ccp (pwm) usart comparators ssp timers 8/16-bit flash (bytes) # single word instructions sram (bytes) eeprom (bytes) pic16f87 7168 4096 368 256 16 n/a 1 y 2 y 2/1 pic16f88 7168 4096 368 256 16 1 1 y 2 y 2/1 18/20/28-pin enhanced flash mc us with nanowatt technology
pic16f87/88 ds30487b-page 2 preliminary ? 2003 microchip technology inc. pin diagrams ra1/an1 ra0/an0 ra7/osc1/clki ra6/osc2/clko v dd rb7/pgd/t1osi rb6/pgc/t1oso/t1cki rb5/ss /tx/ck rb4/sck/scl ra2/an2/cv ref ra3/an3/c1out ra4/t0cki/c2out ra5/mclr /v pp v ss rb0/int/ccp1 (1) rb1/sdi/sda rb2/sdo/rx/dt rb3/pgm/ccp1 (1) 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pic16f87 18-pin dip, soic rb7/an6/pgd/t1osi rb6/an5/pgc/t1oso/t1cki ra7/osc1/clki ra6/osc2/clko v dd rb5/ss /tx/ck rb4/sck/scl rb3/pgm/ccp1 (1) rb2/sdo/rx/dt ra0/an0 ra1/an1 ra4/an4/t0cki/c2out ra5/mclr 1/v pp v ss ra2/an2/cv ref /v ref - ra3/an3/v ref +/c1out rb0/int/ccp1 (1) rb1/sdi/sda 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 av dd av ss 10 11 pic16f88 20-pin ssop 20-pin ssop 18-pin dip & soic ra1/an1 ra0/an0 ra7/osc1/clki ra6/osc2/clko v dd rb7/an6/pgd/t1osi rb6/an5/pgc/t1oso/t1cki rb5/ss /tx/ck rb4/sck/scl ra2/an2/cv ref /v ref - ra3/an3/v ref +/c1out ra4/an4/t0cki/c2out ra5/mclr /v pp v ss rb0/int/ccp1 (1) rb1/sdi/sda rb2/sdo/rx/dt rb3/pgm/ccp1 (1) 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pic16f88 rb7/pgd/t1osi rb6/pgc/t1oso/t1cki ra7/osc1/clki ra6/osc2/clko v dd rb5/ss /tx/ck rb4/sck/scl rb3/pgm/ccp1 (1) rb2/sdo/rx/dt ra0/an0 ra1/an1 ra4/t0cki/c2out ra5/mclr /v pp v ss ra2/an2/cv ref ra3/an3/c1out rb0/int/ccp1 (1) rb1/sdi/sda 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 av dd av ss 10 11 pic16f87 note 1: the ccp1 pin is determined by ccpmx in configuration word 1 register.
? 2003 microchip technology inc. preliminary ds30487b-page 3 pic16f87/88 pin diagrams (cont?d) 16 2 ra2/an2/cv ref ra0/an0 ra4/t0cki/c2out ra5/mclr /v pp nc av ss nc rb0/int/ccp1 (1) rb1/sdi/sda ra3/an3/c1out ra7/osc1/clki ra6/osc2/clko v dd nc av dd rb7/pgd/t1osi rb6/pgc/t1oso/t1cki rb5/ss /tx/ck rb4/sck/scl 7 pic16f87 1 3 6 5 4 15 21 19 20 17 18 22 28 26 27 23 24 25 14 8 10 9 13 12 11 v ss nc nc ra1/an1 rb2/sdo/rx/dt rb3/pgm/ccp1 (1) nc nc nc 16 2 ra2/an2/cv ref /v ref - ra0/an0 ra4/an4/t0cki/c2out ra5/mclr /v pp nc av ss nc rb0/int/ccp1 (1) rb1/sdi/sda ra3/an3/v ref +/c1out ra7/osc1/clki ra6/osc2/clko v dd nc av dd rb7/an6/pgd/t1osi rb6/an5/pgc/t1oso/t1cki rb5/ss /tx/ck rb4/sck/scl 7 pic16f88 1 3 6 5 4 15 21 19 20 17 18 22 28 26 27 23 24 25 14 8 10 9 13 12 11 v ss nc nc ra1/an1 rb2/sdo/rx/dt rb3/pgm/ccp1 (1) nc nc nc 28-pin qfn 28-pin qfn note 1: the ccp1 pin is determined by ccpmx in configuration word 1 register.
pic16f87/88 ds30487b-page 4 preliminary ? 2003 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 5 2.0 memory organization ......................................................................................................... ........................................................ 11 3.0 data eeprom and flash program memory ........................................................................................ ................................... 27 4.0 oscillator configurations ................................................................................................... ......................................................... 35 5.0 i/o ports ................................................................................................................... .................................................................. 51 6.0 timer0 module ............................................................................................................... ............................................................ 67 7.0 timer1 module ............................................................................................................... ............................................................ 71 8.0 timer2 module ............................................................................................................... ............................................................ 79 9.0 capture/compare/pwm (ccp) module ............................................................................................ ......................................... 81 10.0 synchronous serial port (ssp) module ....................................................................................... .............................................. 87 11.0 addressable universal synchronous asynchr onous receiver transmitter (usart)................................................ ................ 97 12.0 analog-to-digital converter (a/d) module ................................................................................... ............................................. 113 13.0 comparator module.......................................................................................................... ........................................................ 121 14.0 comparator voltage reference module ........................................................................................ ........................................... 127 15.0 special features of the cpu ................................................................................................ .................................................... 129 16.0 instruction set summary .................................................................................................... ...................................................... 149 17.0 development support........................................................................................................ ....................................................... 157 18.0 electrical characteristics ................................................................................................. ......................................................... 163 19.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 191 20.0 packaging information...................................................................................................... ........................................................ 193 appendix a: revision history................................................................................................... .......................................................... 199 appendix b: device differences................................................................................................. ........................................................ 199 index .......................................................................................................................... ........................................................................ 201 on-line support................................................................................................................ ................................................................. 209 systems information and upgrade hot line ....................................................................................... ............................................... 209 reader response ................................................................................................................ .............................................................. 210 pic16f87/88 product identification system ...................................................................................... ................................................ 211 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchip?s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, pleas e specify which device, revisi on of silicon and data sheet (inclu de liter- ature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
? 2003 microchip technology inc. preliminary ds30487b-page 5 pic16f87/88 1.0 device overview this document contains device specific information for the operation of the pic16f87/88 devices. additional information may be found in the picmicro ? mid-range mcu reference manual (ds33023) which may be downloaded from the microchip web site. this refer- ence manual should be considered a complementary document to this data sheet, and is highly recom- mended reading for a better understanding of the device architecture and operation of the peripheral modules. the pic16f87/88 belongs to the mid-range family of the picmicro ? devices. block diagrams of the devices are shown in figure 1-1 and figure 1-2. these devices contain features that are new to the pic16 product line: low-power modes: rc_run allows the core and peripherals to be clocked from the intrc, while sec_run allows the core and peripherals to be clocked from the low-power timer1. refer to section 4.7 ?power managed modes? for further details. internal rc oscillator with eight selectable frequencies, including 31.25 khz, 125 khz, 250 khz, 500 khz, 1 mhz, 2 mhz, 4 mhz, and 8 mhz. the intrc can be configured as a primary or secondary clock source. refer to section 4.5 ?internal oscillator block? for further details. the timer1 module current consumption has been greatly reduced from 20 a (previous pic16 devices) to 1.8 a typical (32 khz at 2v), which is ideal for real-time clock applications. refer to section 7.0 ?timer1 module? for further details. extended watchdog timer (wdt) that can have a programmable period from 1 ms to 268s. the wdt has its own 16-bit prescaler. refer to section 15.12 ?watchdog timer (wdt)? for further details. two-speed start-up: when the oscillator is configured for lp, xt, or hs, this feature will clock the device from the intrc while the oscillator is warming up. this, in turn, will enable almost immediate code execution. refer to section 15.12.3 ?two-speed clock start-up mode? for further details. fail-safe clock monitor: this feature will allow the device to continue operation if the primary or secondary clock source fails by switching over to the intrc. the a/d module has a new register for pic16 devices named ansel. this register allows easier configuration of analog or digital i/o pins. table 1-1: available memory in pic16f87/88 devices there are 16 i/o pins that are user configurable on a pin-to-pin basis. some pins are multiplexed with other device functions. these functions include: external interrupt change on portb interrupt timer0 clock input low-power timer1 clock/oscillator capture/compare/pwm 10-bit, 7-channel a/d converter (pic16f88 only) spi?/i 2 c? two analog comparators usart mclr (ra5) can be configured as an input table 1-2 details the pinout of the device with descriptions and details for each pin. device program flash data memory data eeprom pic16f87/88 4k x 14 368 x 8 256 x 8
pic16f87/88 ds30487b-page 6 preliminary ? 2003 microchip technology inc. figure 1-1: pic16f87 device block diagram flash program memory 4k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 368 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clki osc2/clko ra5/mclr v dd , v ss 8 8 brown-out reset note 1: higher order bits are from the status register. 2: the ccp1 pin is determined by ccpmx in configuration word 1 register. 8 3 comparators timer0 data ee 256 bytes timer1 ccp1 timer2 usart porta portb ra4/t0cki/c2out rb0/int/ccp1 (2) ra3/an3/c1out ra2/an2/cv ref ra1/an1 ra0/an0 ra5/mclr /v pp ra6/osc2/clko rb5/ss /tx/ck rb4/sck/scl rb3/pgm/ccp1 (2) rb2/sdo/rx/dt rb1/sdi/sda rb6/pgc/t1oso/t1cki rb7/pgd/t1osi ra7/osc1/clki ssp
? 2003 microchip technology inc. preliminary ds30487b-page 7 pic16f87/88 figure 1-2: pic16f88 device block diagram flash program memory 4k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 368 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clki osc2/clko ra5/mclr v dd , v ss 8 8 brown-out reset note 1: higher order bits are from the status register. 2: the ccp1 pin is determined by ccpmx in configuration word 1 register. 8 3 comparators timer0 data ee 256 bytes timer1 ccp1 timer2 usart porta portb ra4/an4/t0cki/c2out rb0/int/ccp1 (2) ra3/an3/v ref +/c1out ra2/an2/cv ref /v ref - ra1/an1 ra0/an0 ra5/mclr /v pp ra6/osc2/clko rb5/ss /tx/ck rb4/sck/scl rb3/pgm/ccp1 (2) rb2/sdo/rx/dt rb1/sdi/sda rb6/an5/pgc/t1oso/t1cki rb7/an6/pgd/t1osi ra7/osc1/clki 10-bit a/d ssp
pic16f87/88 ds30487b-page 8 preliminary ? 2003 microchip technology inc. table 1-2: pic16f87/88 pinout description pin name pdip/ soic pin# ssop pin# qfn pin# i/o/p type buffer ty pe description porta is a bidirectional i/o port. ra0/an0 ra0 an0 17 19 23 i/o i ttl analog bidirectional i/o pin. analog input channel 0. ra1/an1 ra1 an1 18 20 24 i/o i ttl analog bidirectional i/o pin. analog input channel 1. ra2/an2/cv ref /v ref - ra2 an2 cv ref v ref - (4) 1126 i/o i o i ttl analog analog bidirectional i/o pin. analog input channel 2. comparator v ref output. a/d reference voltage (low) input. ra3/an3/v ref +/c1out ra3 an3 v ref + (4) c1out 2227 i/o i i o ttl analog analog bidirectional i/o pin. analog input channel 3. a/d reference voltage (high) input. comparator 1 output. ra4/an4/t0cki/c2out ra4 an4 (4) t0cki c2out 3328 i/o i i o st analog st bidirectional i/o pin. analog input channel 4. clock input to the tmr0 timer/counter. comparator 2 output. ra5/mclr /v pp ra5 mclr v pp 441 i i p st st ? input pin. master clear (reset). input/programming voltage input. this pin is an active low reset to the device. programming voltage input. ra6/osc2/clko ra6 osc2 clko 15 17 20 i/o o o st ? ? bidirectional i/o pin. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, this pin outputs clko signal which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. ra7/osc1/clki ra7 osc1 clki 16 18 21 i/o i i st st/cmos (3) ? bidirectional i/o pin. oscillator crystal input. external clock source input. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise. 4: pic16f88 devices only. 5: the ccp1 pin is determined by ccpmx in configuration word 1 register.
? 2003 microchip technology inc. preliminary ds30487b-page 9 pic16f87/88 portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int/ccp1 (5) rb0 int ccp1 677 i/o i i/o ttl st (1) st bidirectional i/o pin. external interrupt pin. capture input, compare output, pwm output. rb1/sdi/sda rb1 sdi sda 788 i/o i i/o ttl st st bidirectional i/o pin. spi data in. i 2 c data. rb2/sdo/rx/dt rb2 sdo rx dt 899 i/o o i i/o ttl st bidirectional i/o pin. spi data out. usart asynchronous receive. usart synchronous detect. rb3/pgm/ccp1 (5) rb3 pgm ccp1 91010 i/o i/o i ttl st st bidirectional i/o pin. low-voltage icsp programming enable pin. capture input, compare output, pwm output. rb4/sck/scl rb4 sck scl 10 11 12 i/o i/o i ttl st st bidirectional i/o pin. interrupt-on-change pin. synchronous serial clock input/output for spi. synchronous serial clock input for i 2 c. rb5/ss /tx/ck rb5 ss tx ck 11 12 13 i/o i o i/o ttl ttl bidirectional i/o pin. interrupt-on-change pin. slave select for spi in slave mode. usart asynchronous transmit. usart synchronous clock. rb6/an5/pgc/t1oso/ t1cki rb6 an5 (4) pgc t1oso t1cki 12 13 15 i/o i i/o o i ttl st (2) st st bidirectional i/o pin. interrupt-on-change pin. analog input channel 5. in-circuit debugger and programming clock pin. timer1 oscillator output. timer1 external clock input. rb7/an6/pgd/t1osi rb7 an6 (4) pgd t1osi 13 14 16 i/o i i i ttl st (2) st bidirectional i/o pin. interrupt-on-change pin. analog input channel 6. in-circuit debugger and icsp programming data pin. timer1 oscillator input. v ss 5 5, 6 3, 5 p ? ground reference for logic and i/o pins. v dd 14 15, 16 17, 19 p ? positive supply for logic and i/o pins. table 1-2: pic16f87/88 pinout description (continued) pin name pdip/ soic pin# ssop pin# qfn pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise. 4: pic16f88 devices only. 5: the ccp1 pin is determined by ccpmx in configuration word 1 register.
pic16f87/88 ds30487b-page 10 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 11 pic16f87/88 2.0 memory organization there are two memory blocks in the pic16f87/88 devices. these are the program memory and the data memory. each block has its own bus so access to each block can occur during the same oscillator cycle. the data memory can be further broken down into the general purpose ram and the special function registers (sfrs). the operation of the sfrs that control the ?core? are described here. the sfrs used to control the peripheral modules are described in the section discussing each individual peripheral module. the data memory area also contains the data eeprom memory. this memory is not directly mapped into the data memory but is indirectly mapped. that is, an indi- rect address pointer specifies the address of the data eeprom memory to read/write. the pic16f87/88 device?s 256 bytes of data eeprom memory have the address range 00h-ffh. more details on the eeprom memory can be found in section 3.0 ?data eeprom and flash program memory? . additional information on device memory may be found in the picmicro ? mid-range reference manual (ds33023). 2.1 program memory organization the pic16f87/88 devices have a 13-bit program counter capable of addressing an 8k x 14 program memory space. for the pic16f87/88, the first 4k x 14 (0000h-0fffh) is physically implemented (see figure 2-1). accessing a location above the physically implemented address will cause a wraparound. for example, the same instruction will be accessed at loca- tions 020h, 420h, 820h, c20h, 1020h, 1420h, 1820h, and 1c20h. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: program memory map and stack: pic16f87/88 2.2 data memory organization the data memory is partitioned into multiple banks that contain the general purpose registers and the special function registers. bits rp1 (status<6>) and rp0 (status<5>) are the bank select bits. each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain sfrs. some ?high use? sfrs from one bank may be mirrored in another bank for code reduction and quicker access (e.g., the status register is in banks 0-3). rp1:rp0 bank 00 0 01 1 10 2 11 3 note: eeprom data memory description can be found in section 3.0 ?data eeprom and flash program memory? of this data sheet. pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw 1fffh stack level 2 program memory page 0 07ffh wraps to 0000h - 03ffh page 1 0fffh 1000h 0800h
pic16f87/88 ds30487b-page 12 preliminary ? 2003 microchip technology inc. 2.2.1 general purpose register file the register file can be accessed either directly, or indirectly through the file select register (fsr). figure 2-2: pic16f87 register file map indirect addr. (*) tmr0 pcl status fsr porta portb pclath intcon pir1 option pcl status fsr trisa trisb pclath intcon pie1 pcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations, read as ? 0 ?. * not a physical register. note 1: this register is reserved, maintain this register clear. file address indirect addr. (*) indirect addr. (*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh indirect addr. (*) cvrcon tmr0 option pir2 pie2 general purpose register accesses 70h-7fh trisb portb 96 bytes efh f0h 10ch 10dh 10eh 10fh 110h 18ch 18dh 18eh 18fh 190h eedata eeadr eecon1 eecon2 eedath eeadrh reserved (1) reserved (1) 17fh 1ffh bank 2 bank 3 19fh 1a0h accesses 70h - 7fh 11fh 120h accesses 70h-7fh cmcon osccon general purpose register 80 bytes tmr1l tmr1h t1con tmr2 t2con ccpr1l ccpr1h ccp1con rcsta txreg rcreg pr2 txsta spbrg osctune wdtcon 16fh 170h general purpose register 80 bytes 1efh 1f0h general purpose register 80 bytes general purpose register 16 bytes general purpose register 16 bytes sspbuf sspcon1 sspadd sspstat file address file address file address
? 2003 microchip technology inc. preliminary ds30487b-page 13 pic16f87/88 figure 2-3: pic16f88 register file map indirect addr. (*) tmr0 pcl status fsr porta portb pclath intcon pir1 option pcl status fsr trisa trisb pclath intcon pie1 pcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 file address indirect addr. (*) indirect addr. (*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh indirect addr. (*) tmr0 option pir2 pie2 adresh adcon0 adcon1 general purpose register accesses 70h-7fh trisb portb 96 bytes 10ch 10dh 10eh 10fh 110h 18ch 18dh 18eh 18fh 190h eedata eeadr eecon1 eecon2 eedath eeadrh reserved (1) reserved (1) 17fh 1ffh bank 2 bank 3 19fh 1a0h 11fh 120h cvrcon osccon cmcon adresl tmr1l tmr1h t1con tmr2 ccpr1l ccpr1h ccp1con rcsta txreg rcreg pr2 txsta spbrg t2con osctune wdtcon efh f0h general purpose register 80 bytes 16fh 170h general purpose register 80 bytes 1efh 1f0h general purpose register 80 bytes general purpose register 16 bytes general purpose register 16 bytes accesses 70h - 7fh accesses 70h-7fh sspbuf sspcon1 sspadd sspstat ansel file address file address file address unimplemented data memory locations, read as ? 0 ?. * not a physical register. note 1: this register is reserved, maintain this register clear.
pic16f87/88 ds30487b-page 14 preliminary ? 2003 microchip technology inc. 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 2-1. the special function registers can be classified into two sets: core (cpu) and peripheral. those registers associated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in the peripheral feature section. table 2-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page bank 0 00h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 26, 135 01h tmr0 timer0 module register xxxx xxxx 69 02h (2) pcl program counter (pc) least significant byte 0000 0000 03h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 17 04h (2) fsr indirect data memory address pointer xxxx xxxx 135 05h porta porta data latch when written; porta pins when read (pic16f87) porta data latch when written; porta pins when read (pic16f88) xxxx 0000 xxx0 0000 52 06h portb portb data latch when written; portb pins when read (pic16f87) portb data latch when written; portb pins when read (pic16f88) xxxx xxxx 00xx xxxx 58 07h ? unimplemented ? ? 08h ? unimplemented ? ? 09h ? unimplemented ? ? 0ah (1,2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 135 0bh (2) intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 19, 69, 77 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 21, 77 0dh pir2 osfif cmif ? eeif ? ? ? ? 00-0 ---- 23, 34 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx 77, 83 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx 77, 83 10h t1con ? t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on -000 0000 72, 83 11h tmr2 timer2 module register 0000 0000 80, 85 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 80, 85 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx 90, 95 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 89, 95 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx 83, 85 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx 83, 85 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 81, 83 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 98, 99 19h txreg usart transmit data register 0000 0000 103 1ah rcreg usart receive data register 0000 0000 105 1bh ? unimplemented ? ? 1ch ? unimplemented ? ? 1dh ? unimplemented ? ? 1eh adresh (4) a/d result register high byte xxxx xxxx 120 1fh adcon0 (4) adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 114, 120 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: these registers can be addressed from any bank. 3: ra5 is an input only; the state of the trisa5 bit has no effect and will always read ? 1 ?. 4: pic16f88 device only.
? 2003 microchip technology inc. preliminary ds30487b-page 15 pic16f87/88 bank 1 80h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 26, 135 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 18, 69 82h (2) pcl program counter (pc) least significant byte 0000 0000 135 83h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 17 84h (2) fsr indirect data memory address pointer xxxx xxxx 135 85h trisa trisa7 trisa6 trisa5 (3) porta data direction register (trisa<4:0>) 1111 1111 52, 126 86h trisb portb data direction register 1111 1111 58, 85 87h ? unimplemented ? ? 88h ? unimplemented ? ? 89h ? unimplemented ? ? 8ah (1,2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 135 8bh (2) intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 19, 69, 77 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 20, 80 8dh pie2 osfie cmie ?eeie ? ? ? ? 00-0 ---- 22, 34 8eh pcon ? ? ? ? ? ?por bor ---- --qq 24 8fh osccon ? ircf2 ircf1 ircf0 osts iofs scs1 scs0 -000 0000 40 90h osctune ? ? tun5 tun4 tun3 tun2 tun1 tun0 --00 0000 38 91h ? unimplemented ? ? 92h pr2 timer2 period register 1111 1111 80, 85 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 95 94h sspstat smp cke d/a psr/w ua bf 0000 0000 88, 95 95h ? unimplemented ? ? 96h ? unimplemented ? ? 97h ? unimplemented ? ? 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 97, 99 99h spbrg baud rate generator register 0000 0000 99, 103 9ah ? unimplemented ? 120 9bh ansel (4) ? ans6 ans5 ans4 ans3 ans2 ans1 ans0 -111 1111 120 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 121, 126, 128 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 126, 128 9eh adresl (4) a/d result register low byte xxxx xxxx 120 9fh adcon1 (4) adfm adcs2 vcfg1 vcfg0 ? ? ? ? 0000 ---- 52, 115, 120 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: these registers can be addressed from any bank. 3: ra5 is an input only; the state of the trisa5 bit has no effect and will always read ? 1 ?. 4: pic16f88 device only.
pic16f87/88 ds30487b-page 16 preliminary ? 2003 microchip technology inc. bank 2 100h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 26, 135 101h tmr0 timer0 module register xxxx xxxx 69 102h (2) pcl program counter's (pc) least significant byte 0000 0000 135 103h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 17 104h (2) fsr indirect data memory address pointer xxxx xxxx 135 105h wdtcon ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 swdten ---0 1000 142 106h portb portb data latch when written; portb pins when read xxxx xxxx 58 107h ? unimplemented ? ? 108h ? unimplemented ? ? 109h ? unimplemented ? ? 10ah (1,2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 135 10bh (2) intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 19, 69, 77 10ch eedata eeprom data register low byte xxxx xxxx 34 10dh eeadr eeprom address register low byte xxxx xxxx 34 10eh eedath ? ? eeprom data register high byte --xx xxxx 34 10fh eeadrh ? ? ? ? eeprom address register high byte ---- xxxx 34 bank 3 180h (2) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 135 181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 18, 69 182h (2) pcl program counter (pc) least significant byte 0000 0000 135 183h (2) status irp rp1 rp0 to pd zdcc 0001 1xxx 17 184h (2) fsr indirect data memory address pointer xxxx xxxx 135 185h ? unimplemented ? ? 186h trisb portb data direction register 1111 1111 58, 83 187h ? unimplemented ? ? 188h ? unimplemented ? ? 189h ? unimplemented ? ? 18ah (1,2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 135 18bh (2) intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 19, 69, 77 18ch eecon1 eepgd ? ? free wrerr wren wr rd x--x x000 28, 34 18dh eecon2 eeprom control register2 (not a physical register) ---- ---- 34 18eh ? reserved, maintain clear 0000 0000 ? 18fh ? reserved, maintain clear 0000 0000 ? table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: these registers can be addressed from any bank. 3: ra5 is an input only; the state of the trisa5 bit has no effect and will always read ? 1 ?. 4: pic16f88 device only.
? 2003 microchip technology inc. preliminary ds30487b-page 17 pic16f87/88 2.2.2.1 status register the status register, shown in register 2-1, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as ? 000u u1uu ? (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register because these instructions do not affect the z, c or dc bits from the status register. for other instructions not affecting any status bits, see section 16.0 ?instruction set summary? . register 2-1: status register (address 03h, 83h, 103h, 183h) note: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdc c bit 7 bit 0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5 rp<1:0>: register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit ( addwf , addlw , sublw and subwf instructions) (1) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c: carry/borrow bit ( addwf , addlw , sublw and subwf instructions) (1,2) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow, the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. 2: for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 18 preliminary ? 2003 microchip technology inc. 2.2.2.2 option register the option register is a readable and writable regis- ter that contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assignable register known also as the prescaler), the external int interrupt, tmr0, and the weak pull-ups on portb. register 2-2: option register (address 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. although the pres- caler can be assigned to either the wdt or timer0, but not both, a new divide counter is implemented in the wdt circuit to give multiple wdt time-out selection. this allows tmr0 and wdt to each have their own scaler. refer to section 15.12 ?watchdog timer (wdt)? for further details. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs: tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit value tmr0 rate wdt rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128
? 2003 microchip technology inc. preliminary ds30487b-page 19 pic16f87/88 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter that contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 2-3: intcon: interrupt control register (address 0bh, 8bh, 10bh, 18bh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie tmr0ie inte rbie tmr0if intf rbif bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte: rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf: rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 20 preliminary ? 2003 microchip technology inc. 2.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. register 2-4: pie1: peripheral interrupt enable register 1 (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?adie (1) rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 adie: a/d converter interrupt enable bit (1) 1 = enabled 0 = disabled note 1: this bit is only implemented on the pic16f88. the bit will read ? 0 ? on the pic16f87. bit 5 rcie: usart receive interrupt enable bit 1 = enabled 0 = disabled bit 4 txie: usart transmit interrupt enable bit 1 = enabled 0 = disabled bit 3 sspie: synchronous serial port (ssp) interrupt enable bit 1 = enabled 0 = disabled bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enabled 0 = disabled bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enabled 0 = disabled bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enabled 0 = disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 21 pic16f87/88 2.2.2.5 pir1 register this register contains the individual flag bits for the peripheral interrupts. register 2-5: pir1: peripheral interrupt status register 1 (address 0ch) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. u-0 r/w-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 ?adif (1) rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 adif: a/d converter interrupt flag bit (1) 1 = the a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete note 1: this bit is only implemented on the pic16f88. the bit will read ? 0 ? on the pic16f87. bit 5 rcif: usart receive interrupt flag bit 1 = the usart receive buffer is full (cleared by reading rcreg) 0 = the usart receive buffer is not full bit 4 txif: usart transmit interrupt flag bit 1 = the usart transmit buffer is empty (cleared by writing to txreg) 0 = the usart transmit buffer is full bit 3 sspif: synchronous serial port (ssp) interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if: ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if: tmr2 to pr2 interrupt flag bit 1 = a tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = the tmr1 register overflowed (must be cleared in software) 0 = the tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 22 preliminary ? 2003 microchip technology inc. 2.2.2.6 pie2 register the pie2 register contains the individual enable bit for the eeprom write operation interrupt. register 2-6: pie2: peripheral interrupt enable register 2 (address 8dh) r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 osfie cmie ? eeie ? ? ? ? bit 7 bit 0 bit 7 osfie: oscillator fail interrupt enable bit 1 = enabled 0 = disabled bit 6 cmie: comparator interrupt enable bit 1 = enabled 0 = disabled bit 5 unimplemented: read as ? 0 ? bit 4 eeie: eeprom write operation interrupt enable bit 1 = enabled 0 = disabled bit 3-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 23 pic16f87/88 2.2.2.7 pir2 register the pir2 register contains the flag bit for the eeprom write operation interrupt. . register 2-7: pir2: peripheral interrupt status register 2 (address 0dh) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 osfif cmif ? eeif ? ? ? ? bit 7 bit 0 bit 7 osfif: oscillator fail interrupt flag bit 1 = system oscillator failed, clock input has changed to intrc (must be cleared in software) 0 = system clock operating bit 6 cmif: comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed bit 5 unimplemented: read as ? 0 ? bit 4 eeif: eeprom write operation interrupt flag bit 1 = the write operation completed (must be cleared in software) 0 = the write operation is not complete or has not been started bit 3-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 24 preliminary ? 2003 microchip technology inc. 2.2.2.8 pcon register the power control (pcon) register contains a flag bit to allow differentiation between a power-on reset (por), a brown-out reset, an external mclr reset and wdt reset. register 2-8: pcon: power control regist er (address 8eh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. note: bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a ?don't care? and is not necessarily predictable if the brown- out circuit is disabled (by clearing the boren bit in the configuration word register). u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-x ? ? ? ? ? ?por bor bit 7 bit 0 bit 7-2 unimplemented: read as ? 0 ? bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 25 pic16f87/88 2.3 pcl and pclath the program counter (pc) is 13-bits wide. the low byte comes from the pcl register which is a readable and writable register. the upper bits (pc<12:8>) are not readable but are indirectly writable through the pclath register. on any reset, the upper bits of the pc will be cleared. figure 2-4 shows the two situations for the loading of the pc. the upper example in the fig- ure shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower example in the fig- ure shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). figure 2-4: loading of pc in different situations 2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to the application note, ?an556, implementing a table read? . 2.3.2 stack the pic16f87/88 family has an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging all pic16f87/88 devices are capable of addressing a continuous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruc- tion, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is executed, the entire 13-bit pc is popped off the stack. therefore, manipulation of the pclath<4:3> bits is not required for the return instructions (which pops the address from the stack). example 2-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt service routine (if interrupts are used). example 2-1: call of a subroutine in page 1 from page 0 pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu goto,call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch 87 2 pclath pch pcl pcl as destination pcl note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw and retfie instructions, or the vectoring to an interrupt address. note: the contents of the pclath register are unchanged after a return or retfie instruction is executed. the user must rewrite the contents of the pclath regis- ter for any subsequent subroutine calls or goto instructions. org 0x500 bcf pclath,4 bsf pclath,3 ;select page 1 ;(800h-fffh) call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : org 0x900 ;page 1 (800h-fffh) sub1_p1 : ;called subroutine ;page 1 (800h-fffh) : return ;return to ;call subroutine ;in page 0 ;(000h-7ffh)
pic16f87/88 ds30487b-page 26 preliminary ? 2003 microchip technology inc. 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister, fsr. reading the indf register itself, indirectly (fsr = 0 ) will read 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>) as shown in figure 2-5. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-2. example 2-2: indirect addressing figure 2-5: direct/indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue note 1: for register file map detail, see figure 2-2 or figure 2-3. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h
? 2003 microchip technology inc. preliminary ds30487b-page 27 pic16f87/88 3.0 data eeprom and flash program memory the data eeprom and flash program memory are readable and writable during normal operation (over the full v dd range). this memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers. there are six sfrs used to read and write this memory: eecon1 eecon2 eedata eedath eeadr eeadrh when interfacing the data memory block, eedata holds the 8-bit data for read/write and eeadr holds the address of the eeprom location being accessed. the pic16f87/88 devices have 256 bytes of data eeprom with an address range from 00h to 0ffh. when writing to unimplemented locations, the charge pump will be turned off. when interfacing the program memory block, the eedata and eedath registers form a two-byte word that holds the 14-bit data for read/write, and the eeadr and eeadrh registers form a two-byte word that holds the 13-bit address of the eeprom location being accessed. the pic16f87/88 devices have 4k words of program flash with an address range from 0000h to 0fffh. addresses above the range of the respective device will wraparound to the beginning of program memory. the eeprom data memory allows single byte read and write. the flash program memory allows single word reads and four-word block writes. program mem- ory writes must first start with a 32-word block erase, then write in 4-word blocks. a byte write in data eeprom memory automatically erases the location and writes the new data (erase before write). the write time is controlled by an on-chip timer. the write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device for byte or word operations. when the device is code protected, the cpu may continue to read and write the data eeprom memory. depending on the settings of the write protect bits, the device may or may not be able to write certain blocks of the program memory; however, reads of the program memory are allowed. when code protected, the device programmer can no longer access data or program memory; this does not inhibit internal reads or writes. 3.1 eeadr and eeadrh the eeadrh:eeadr register pair can address up to a maximum of 256 bytes of data eeprom, or up to a maximum of 8k words of program eeprom. when selecting a data address value, only the lsbyte of the address is written to the eeadr register. when select- ing a program address value, the msbyte of the address is written to the eeadrh register and the lsbyte is written to the eeadr register. if the device contains less memory than the full address reach of the address register pair, the most significant bits of the registers are not implemented. for example, if the device has 128 bytes of data eeprom, the most significant bit of eeadr is not implemented on access to data eeprom. 3.2 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. control bit eepgd determines if the access will be a program or data memory access. when clear, as it is when reset, any subsequent operations will operate on the data memory. when set, any subsequent operations will operate on the program memory. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set in software. they are cleared in hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write or erase operation. on power-up, the wren bit is clear. the wrerr bit is set when a write (or erase) operation is interrupted by a mclr , or a wdt time-out reset dur- ing normal operation. in these situations, following reset, the user can check the wrerr bit and rewrite the location. the data and address will be unchanged in the eedata and eeadr registers. interrupt flag bit, eeif in the pir2 register, is set when write is complete. it must be cleared in software. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the eeprom write sequence.
pic16f87/88 ds30487b-page 28 preliminary ? 2003 microchip technology inc. register 3-1: eecon1: eeprom access control register 1 (address 18ch) r/w-x u-0 u-0 r/w-x r/w-x r/w-0 r/s-0 r/s-0 eepgd ? ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd : program/data eeprom select bit 1 = accesses program memory 0 = accesses data memory bit 6-5 unimplemented: read as ? 0 ? bit 4 free: eeprom forced row erase bit 1 = erase the program memory row addressed by eeadrh:eeadr on the next wr command 0 = perform write only bit 3 wrerr: eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr or any wdt reset during normal operation) 0 = the write operation completed bit 2 wren: eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the eeprom bit 1 wr: write control bit 1 = initiates a write cycle. the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software. 0 = write cycle to the eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read, rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate an eeprom read legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = set only - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 29 pic16f87/88 3.3 reading data eeprom memory to read a data memory location, the user must write the address to the eeadr register, clear the eepgd con- trol bit (eecon1<7>) and then set control bit rd (eecon1<0>). the data is available in the very next cycle in the eedata register; therefore, it can be read in the next instruction (see example 3-1). eedata will hold this value until another read or until it is written to by the user (during a write operation). the steps to reading the eeprom data memory are: 1. write the address to eeadr. make sure that the address is not larger than the memory size of the device. 2. clear the eepgd bit to point to eeprom data memory. 3. set the rd bit to start the read operation. 4. read the data from the eedata register. example 3-1: data eeprom read 3.4 writing to data eeprom memory to write an eeprom data location, the user must first write the address to the eeadr register and the data to the eedata register. then, the user must follow a specific write sequence to initiate the write for each byte. the write will not initiate if the write sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. we strongly recommend that interrupts be disabled during this code segment (see example 3-2). additionally, the wren bit in eecon1 must be set to enable write. this mechanism prevents accidental writes to data eeprom due to errant (unexpected) code execution (i.e., lost programs). the user should keep the wren bit clear at all times except when updating eeprom. the wren bit is not cleared by hardware after a write sequence has been initiated, clearing the wren bit will not affect this write cycle. the wr bit will be inhibited from being set unless the wren bit is set. at the completion of the write cycle, the wr bit is cleared in hardware and the ee write complete interrupt flag bit (eeif) is set. the user can either enable this interrupt or poll this bit. eeif must be cleared by software. the steps to write to eeprom data memory are: 1. if step 10 is not implemented, check the wr bit to see if a write is in progress. 2. write the address to eeadr. make sure that the address is not larger than the memory size of the device. 3. write the 8-bit data value to be programmed in the eedata register. 4. clear the eepgd bit to point to eeprom data memory. 5. set the wren bit to enable program operations. 6. disable interrupts (if enabled). 7. execute the special five instruction sequence: write 55h to eecon2 in two steps (first to w, then to eecon2). write aah to eecon2 in two steps (first to w, then to eecon2). set the wr bit. 8. enable interrupts (if using interrupts). 9. clear the wren bit to disable program operations. 10. at the completion of the write cycle, the wr bit is cleared and the eeif interrupt flag bit is set (eeif must be cleared by firmware). if step 1 is not implemented, then firmware should check for eeif to be set, or wr to clear, to indicate the end of the program cycle. example 3-2: data eeprom write banksel eeadr ; select bank of eeadr movf addr,w ; movwf eeadr ; data memory address ; to read banksel eecon1 ; select bank of eecon1 bcf eecon1,eepgd ; point to data memory bsf eecon1,rd ; ee read banksel eedata ; select bank of eedata movf eedata,w ; w = eedata banksel eecon1 ; select bank of ; eecon1 btfsc eecon1,wr ; wait for write goto $-1 ; to complete banksel eeadr ; select bank of ; eeadr movf addr,w ; movwf eeadr ; data memory ; address to write movf value,w ; movwf eedata ; data memory value ; to write banksel eecon1 ; select bank of ; eecon1 bcf eecon1,eepgd; point to data ; memory bsf eecon1,wren ; enable writes bcf intcon,gie ; disable ints. movlw 55h ; movwf eecon2 ; write 55h movlw aah ; movwf eecon2 ; write aah bsf eecon1,wr ; set wr bit to ; begin write bsf intcon,gie ; enable ints. bcf eecon1,wren ; disable writes required sequence
pic16f87/88 ds30487b-page 30 preliminary ? 2003 microchip technology inc. 3.5 reading flash program memory to read a program memory location, the user must write two bytes of the address to the eeadr and eeadrh registers, set the eepgd control bit (eecon1<7>), and then set control bit rd (eecon1<0>). once the read control bit is set, the program memory flash controller will use the second instruction cycle to read the data. this causes the second instruction immediately following the ? bsf eecon1,rd ? instruction to be ignored. the data is available in the very next cycle in the eedata and eedath registers; therefore, it can be read as two bytes in the following instructions. eedata and eedath registers will hold this value until another read or until it is written to by the user (during a write operation). example 3-3: flash program read 3.6 erasing flash program memory the minimum erase block is 32 words. only through the use of an external programmer, or through icsp control, can larger blocks of program memory be bulk erased. word erase in the flash array is not supported. when initiating an erase sequence from the microcon- troller itself, a block of 32 words of program memory is erased. the most significant 11 bits of the eeadrh:eeadr point to the block being erased. eeadr< 4:0> are ignored. the eecon1 register commands the erase operation. the eepgd bit must be set to point to the flash pro- gram memory. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. for protection, the write initiate sequence for eecon2 must be used. after the ? bsf eecon1,wr ? instruction, the processor requires two cycles to setup the erase operation. the user must place two nop instructions after the wr bit is set. the processor will halt internal operations for the typical 2 ms, only during the cycle in which the erase takes place. this is not sleep mode, as the clocks and peripherals will continue to run. after the erase cycle, the processor will resume operation with the third instruction after the eecon1 write instruction. 3.6.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory location is: 1. load eeadrh:eeadr with address of row being erased. 2. set eepgd bit to point to program memory, set wren bit to enable writes, and set free bit to enable the erase. 3. disable interrupts. 4. write 55h to eecon2. 5. write aah to eecon2. 6. set the wr bit. this will begin the row erase cycle. 7. the cpu will stall for duration of the erase. banksel eeadrh ; select bank of eeadrh movf addrh, w ; movwf eeadrh ; ms byte of program ; address to read movf addrl, w ; movwf eeadr ; ls byte of program ; address to read banksel eecon1 ; select bank of eecon1 bsf eecon1, eepgd ; point to program ; memory bsf eecon1, rd ; ee read ; nop ; any instructions ; here are ignored as nop ; program memory is ; read in second cycle ; after bsf eecon1,rd banksel eedata ; select bank of eedata movf eedata, w ; datal = eedata movwf datal ; movf eedath, w ; datah = eedath movwf datah ;
? 2003 microchip technology inc. preliminary ds30487b-page 31 pic16f87/88 example 3-4: erasing a flash program memory row banksel eeadrh ; select bank of eeadrh movf addrh, w ; movwf eeadrh ; ms byte of program address to erase movf addrl, w ; movwf eeadr ; ls byte of program address to erase erase_row banksel eecon1 ; select bank of eecon1 bsf eecon1, eepgd ; point to program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation ; bcf intcon, gie ; disable interrupts (if using) movlw 55h ; movwf eecon2 ; write 55h movlw aah ; movwf eecon2 ; write aah bsf eecon1, wr ; start erase (cpu stall) nop ; any instructions here are ignored as processor ; halts to begin erase sequence nop ; processor will stop here and wait for erase complete ; after erase processor continues with 3rd instruction bcf eecon1, wren ; disable writes bsf intcon, gie ; enable interrupts (if using)
pic16f87/88 ds30487b-page 32 preliminary ? 2003 microchip technology inc. 3.7 writing to flash program memory flash program memory may only be written to if the destination address is in a segment of memory that is not write protected, as defined in bits wrt1:wrt0 of the device configuration word (register 15-1). flash program memory must be written in four-word blocks. a block consists of four words with sequential addresses, with a lower boundary defined by an address, where eeadr<1:0> = 00 . at the same time, all block writes to program memory are done as write only operations. the program memory must first be erased. the write operation is edge-aligned, and cannot occur across boundaries. to write to the program memory, the data must first be loaded into the buffer registers. there are four 14-bit buffer registers and they are addressed by the low 2 bits of eeadr. loading data into the buffer registers is accomplished via the eeadr, eeadt, eecon1 and eecon2 registers as follows: set eecon1 pgd and wren write address to eeadrh:eeadr write data to eedata:eedath write 55, aa to eecon2 set wr bit in eecon1 there are 4 buffer register words and all four locations must be written to with correct data. after the ? bsf eecon1,wr ? instruction, if eeadr xxxxxx11 , then a short write will occur. this short write only transfers the data to the buffer reg- ister. the wr bit will be cleared in hardware after 1 cycle. the core will not halt and there will be no eewhlt signal generated. after the ? bsf eecon1,wr ? instruction, if eeadr = xxxxxx11 , then a long write will occur. this will simultaneously transfer the data from eedath:eedata to the buffer registers and begin the write of all four words. the processor will execute the next instruction and then ignore the subsequent instruction. the user should place nop instructions into the second words. the processor will then halt internal operations for typically 2 msec in which the write takes place. this is not sleep mode, as the clocks and peripherals will continue to run. after the write cycle, the processor will resume operation with the 3rd instruction after the eecon1 write instruction. after each long write, the 4 buffer registers will be reset to 3fff. figure 3-1: block writes to flash program memory 14 14 14 14 program memory buffer register eeadr<1:0> = 00 buffer register eeadr<1:0> = 01 buffer register eeadr<1:0> = 10 buffer register eeadr<1:0> = 11 eedata eedath 75 07 0 6 8 first word of block to be written to flash automatically after this word is written transferred all buffers are
? 2003 microchip technology inc. preliminary ds30487b-page 33 pic16f87/88 an example of the complete four-word write sequence is shown in example 3-5. the initial address is loaded into the eeadrh:eeadr register pair; the four words of data are loaded using indirect addressing, assuming that a row erase sequence has already been performed. example 3-5: writing to flash program memory ; this write routine assumes the following: ; 1. the 32 words in the erase block have already been erased. ; 2. a valid starting address (the least significant bits = '00') is loaded into eeadrh:eeadr ; 3. this example is starting at 0x100, this is an application dependent setting. ; 4. the 8 bytes (4 words) of data are loaded, starting at an address in ram called array. ; 5. this is an example only, location of data to program is application dependent. ; 6. word_block is located in data memory. banksel eecon1 ;prepare for write procedure bsf eecon1,eepgd ;point to program memory bsf eecon1,wren ;allow write cycles banksel word_block movlw .4 movwf word_block ;prepare for 4 words to be written banksel eeadrh ;start writing at 0x100 movlw 0x01 movwf eeadrh ;load high address movlw 0x00 movwf eeadr ;load low address banksel array movlw array ;initialize fsr to start of data movwf fsr loop banksel eedata movf indf,w ;indirectly load eedata movwf eedata incf fsr,f ;increment data pointer movf indf,w ;indirectly load eedath movwf eedath incf fsr,f ;increment data pointer banksel eecon1 movlw 0x55 ;required sequence movwf eecon2 movlw 0xaa movwf eecon2 bsf eecon1,wr ;set wr bit to begin write nop ;instructions here are ignored as processor nop banksel eeadr incf eeadr,f ;load next word address banksel word_block decfsz word_block,f ;have 4 words been written? goto loop ;no, continue with writing banksel eecon1 bcf eecon1,wren ;yes, 4 words complete, disable writes bsf intcon,gie ;enable interrupts required sequence
pic16f87/88 ds30487b-page 34 preliminary ? 2003 microchip technology inc. 3.8 protection against spurious write there are conditions when the device should not write to the data eeprom memory. to protect against spu- rious eeprom writes, various mechanisms have been built-in. on power-up, wren is cleared. also, the power-up timer (72 ms duration) prevents an eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. 3.9 operation during code protect when the data eeprom is code protected, the micro- controller can read and write to the eeprom normally. however, all external access to the eeprom is disabled. external write access to the program memory is also disabled. when program memory is code protected, the micro- controller can read and write to program memory nor- mally, as well as execute instructions. writes by the device may be selectively inhibited to regions of the memory depending on the setting of bits wrt1:wrt0 of the configuration word (see section 15.1 ?configu- ration bits? for additional information). external access to the memory is also disabled. table 3-1: registers/bits associated with data eeprom and flash program memories address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 10ch eedata eeprom/flash data register low byte xxxx xxxx uuuu uuuu 10dh eeadr eeprom/flash address register low byte xxxx xxxx uuuu uuuu 10eh eedath ? ? eeprom/flash data register high byte --xx xxxx --uu uuuu 10fh eeadrh ? ? ? ? ? eeprom/flash address register high byte ---- -xxx ---- -uuu 18ch eecon1 eepgd ? ? free wrerr wren wr rd x--x x000 x--x q000 18dh eecon2 eeprom control register 2 (not a physical register) ---- ---- ---- ---- 0dh pir2 osfif cmif ? eeif ? ? ? ? 00-0 ---- 00-0 ---- 8dh pie2 osfie cmie ?eeie ? ? ? ? 00-0 ---- 00-0 ---- legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends upon condition. shaded cells are not used by data eeprom or flash program memory.
? 2003 microchip technology inc. preliminary ds30487b-page 35 pic16f87/88 4.0 oscillator configurations 4.1 oscillator types the pic16f87/88 can be operated in eight different oscillator modes. the user can program three configu- ration bits (f osc 2:f osc 0) to select one of these eight modes (modes 5-8 are new pic16 oscillator configurations): 1. lp low-power crystal 2. xt crystal/resonator 3. hs high-speed crystal/resonator 4. rc external resistor/capacitor with f osc /4 output on ra6 5. rcio external resistor/capacitor with i/o on ra6 6. intio1 internal oscillator with f osc /4 output on ra6 and i/o on ra7 7. intio2 internal oscillator with i/o on ra6 and ra7 8. ecio external clock with i/o on ra6 4.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clki and osc2/clko pins to establish oscillation (see figure 4-1 and figure 4-2). the pic16f87/88 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. figure 4-1: crystal operation (hs, xt, or lp osc configuration) table 4-1: capacitor selection for crystal oscillator (for design guidance only) note1: see table 4-1 for typical values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the crystal chosen (typically between 2 m ? to 10 m ?) . c1 (1) c2 (1) xtal osc2 r s (2) osc1 r f (3) sleep to internal logic pic16f87/88 osc type crystal freq typical capacitor values tested: c1 c2 lp 32 khz 33 pf 33 pf xt 200 khz 56 pf 56 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15 pf 15 pf 20 mhz 15 pf 15 pf capacitor values are for design guidance only. these capacitors were tested with the crystals listed below for basic start-up and operation. these values were not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following this table for additional information. note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each crystal has its own character- istics, the user should consult the crystal manufacturer for appropriate values of external components. 3: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 4: always verify oscillator performance over the v dd and temperature range that is expected for the application.
pic16f87/88 ds30487b-page 36 preliminary ? 2003 microchip technology inc. figure 4-2: ceramic resonator operation (hs or xt osc configuration) table 4-2: ceramic resonators (for design guidance only) 4.3 external clock input the ecio oscillator mode requires an external clock source to be connected to the osc1 pin. there is no oscillator start-up time required after a power-on reset, or after an exit from sleep mode. in the ecio oscillator mode, the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 4-3 shows the pin connections for the ecio oscillator mode. figure 4-3: external clock input operation (ecio configuration) typical capacitor values used: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 56 pf 47 pf 33 pf 56 pf 47 pf 33 pf hs 8.0 mhz 16.0 mhz 27 pf 22 pf 27 pf 22 pf capacitor values are for design guidance only. these capacitors were tested with the resonators listed below for basic start-up and operation. these values were not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following this table for additional information. note: when using resonators with frequencies above 3.5 mhz, the use of hs mode, rather than xt mode, is recommended. hs mode may be used at any v dd for which the controller is rated. if hs is selected, it is possible that the gain of the oscillator will overdrive the resonator. therefore, a series resistor should be placed between the osc2 pin and the resonator. as a good starting point, the recommended value of r s is 330 ?. note 1: see table 4-2 for typical values of c1 and c2. 2: a series resistor (r s ) may be required. 3: r f varies with the resonator chosen (typically between 2 m ? to 10 m ?) . c1 (1) c2 (1) res osc2 r s (2) osc1 r f (3) sleep to internal logic pic16f87/88 osc1/clki i/o (osc2) ra6 clock from ext. system pic16f87/88
? 2003 microchip technology inc. preliminary ds30487b-page 37 pic16f87/88 4.4 rc oscillator for timing insensitive applications, the ?rc? and ?rcio? device options offer additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) val- ues, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation. furthermore, the dif- ference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 4-4 shows how the r/c combination is connected. in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 4-4: rc oscillator mode the rcio oscillator mode (figure 4-5) functions like the rc mode, except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 4-5: rcio oscillator mode 4.5 internal oscillator block the pic16f87/88 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system?s clock source. this can eliminate the need for external oscillator circuits on the osc1 and/or osc2 pins. the main output (intosc) is an 8 mhz clock source, which can be used to directly drive the system clock. it also drives the intosc postscaler which can provide a range of six clock frequencies from 125 khz to 4 mhz. the other clock source is the internal rc oscillator (intrc) which provides a 31.25 khz (32 s nominal period) output. the intrc oscillator is enabled by selecting the intrc as the system clock source, or when any of the following are enabled: power-up timer watchdog timer two-speed start-up fail-safe clock monitor these features are discussed in greater detail in section 15.0 ?special features of the cpu? . the clock source frequency (intosc direct, intrc direct, or intosc postscaler) is selected by configuring the ircf bits of the osccon register (page 40). osc2/clko c ext r ext pic16f87/88 osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf c ext r ext pic16f87/88 osc1 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf i/o (osc2) ra6 note: throughout this data sheet, when referring specifically to a generic clock source, the term ?intrc? may also be used to refer to the clock modes using the internal oscilla- tor block. this is regardless of whether the actual frequency used is intosc (8 mhz), the intosc postscaler, or intrc (31.25 khz).
pic16f87/88 ds30487b-page 38 preliminary ? 2003 microchip technology inc. 4.5.1 intrc modes using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, after which it can be used for digital i/o. two distinct configurations are available: in intio1 mode, the osc2 pin outputs f osc /4, while osc1 functions as ra7 for digital input and output. in intio2 mode, osc1 functions as ra7 and osc2 functions as ra6, both for digital input and output. 4.5.2 osctune register the internal oscillator?s output has been calibrated at the factory but can be adjusted in the application. this is done by writing to the osctune register (register 4-1). the tuning sensitivity is constant throughout the tuning range. the osctune register has a tuning range of 12.5%. when the osctune register is modified, the intosc and intrc frequencies will begin shifting to the new fre- quency. the intrc clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 s = 256 s); the intosc clock will stabilize within 1 ms. code execu- tion continues during this shift. there is no indication that the shift has occurred. operation of features that depend on the 31.25 khz intrc clock source frequency, such as the wdt, fail-safe clock monitor and peripherals, will also be affected by the change in frequency. register 4-1: osctune: oscillator tuning register (address 90h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun5 tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frequency tuning bits 011111 = maximum frequency 011110 = 000001 = 000000 = center frequency. oscillator module is running at the calibrated frequency. 111111 = 100000 = minimum frequency legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 39 pic16f87/88 4.6 clock sources and oscillator switching the pic16f87/88 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. pic16f87/88 devices offer three alternate clock sources. when enabled, these give additional options for switching to the various power managed operating modes. essentially, there are three clock sources for these devices: primary oscillators secondary oscillators internal oscillator block (intrc) the primary oscillators include the external crystal and resonator modes, the external rc modes, the external clock mode and the internal oscillator block. the particular mode is defined on por by the contents of configuration word 1. the details of these modes are covered earlier in this chapter. the secondary oscillators are those external sources not connected to the osc1 or osc2 pins. these sources may continue to operate even after the controller is placed in a power managed mode. pic16f87/88 devices offer the timer1 oscillator as a secondary oscillator. this oscillator continues to run when a sleep instruction is executed, and is often the time base for functions such as a real-time clock. most often, a 32.768 khz watch crystal is connected between the rb6/t1oso and rb7/t1osi pins. like the lp mode oscillator circuit, loading capacitors are also connected from each pin to ground. the timer1 oscillator is discussed in greater detail in section 7.6 ?timer1 oscillator? . in addition to being a primary clock source, the internal oscillator block is available as a power managed mode clock source. the 31.25 khz intrc source is also used as the clock source for several special fea- tures, such as the wdt, fail-safe clock monitor, power-up timer, and two-speed start-up. the clock sources for the pic16f87/88 devices are shown in figure 4-6. see section 7.0 ?timer1 mod- ule? for further details of the timer1 oscillator. see section 15.1 ?configuration bits? for configuration register details. 4.6.1 osccon register the osccon register (register 4-2) controls several aspects of the system clock?s operation, both in full power operation and in power managed modes. the system clock select bits, scs1:scs0, select the clock source that is used when the device is operating in power managed modes. when the bits are cleared (scs<1:0> = 00 ), the system clock source comes from the main oscillator that is selected by the f osc 2:f osc 0 configuration bits in configuration regis- ter 1. when the bits are set in any other manner, the system clock source is provided by the timer1 oscilla- tor (scs1:scs0 = 01 ), or from the internal oscillator block (scs1:scs0 = 10 ). after a reset, scs<1:0> are always set to ? 00 ?. the internal oscillator select bits, ircf2:ircf0, select the frequency output of the internal oscillator block that is used to drive the system clock. the choices are the intrc source (31.25 khz), the intosc source (8 mhz), or one of the six frequencies derived from the intosc postscaler (125 khz to 4 mhz). changing the configuration of these bits has an immediate change on the internal oscillator?s output. the osts and iofs bits indicate the status of the pri- mary oscillator and intosc source; these bits are set when their respective oscillators are stable. in particu- lar, osts indicates that the oscillator start-up timer has timed out. 4.6.2 clock switching clock switching will occur for the following reasons: the fcmen (config2<0>) bit is set, the device is running from the primary oscillator, and the primary oscillator fails. the clock source will be 31.25 khz intrc. the fcmen bit is set, the device is running from the t1osc and t1osc fails. the clock source will be 31.25 khz intrc. following a wake-up due to a reset or a por, when the device is configured for two-speed start-up mode, switching will occur between the intrc and the system clock defined by the f osc <2:0> bits. a wake-up from sleep occurs due to interrupt or wdt wake-up and two-speed start-up is enabled. if the primary clock is xt, hs, or lp, the clock will switch between the intrc and the pri- mary system clock after 1024 clocks (ost) and 8 clocks of the primary oscillator. this is conditional upon the scs bits being set equal to ? 00 ?. scs bits are modified from their original value. ircf bits are modified from their original value. note: the instruction to immediately follow the modification of scs<1:0> will have an instruction time (t cy ) based on the previ- ous clock source. this should be taken into consideration when developing time dependant code. note: because the scs bits are cleared on any reset, no clock switching will occur on a reset unless the two-speed start-up is enabled and the primary clock is xt, hs, or lp. the device will wait for the primary clock to become stable before execution begins (two-speed start-up disabled).
pic16f87/88 ds30487b-page 40 preliminary ? 2003 microchip technology inc. 4.6.3 clock transition and wdt when clock switching is performed, the watchdog timer is disabled because the watchdog ripple counter is used as the oscillator start-up timer. once the clock transition is complete (i.e., new oscilla- tor selection switch has occurred), the watchdog counter is re-enabled with the counter reset. this allows the user to synchronize the watchdog timer to the start of execution at the new clock frequency. register 4-2: osccon: oscillator control regi ster (address 8fh) note: the ost is only used when switching to xt, hs, and lp oscillator modes. u-0 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 ? ircf2 ircf1 ircf0 osts (1) iofs scs1 scs0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-4 ircf<2:0>: internal rc oscillator frequency select bits 000 = 31.25 khz 001 = 125 khz 010 = 250 khz 011 = 500 khz 100 = 1 mhz 101 = 2 mhz 110 = 4 mhz 111 = 8 mhz bit 3 osts: oscillator start-up time-out status bit (1) 1 = device is running from the primary system clock 0 = device is running from t1osc or intrc as a secondary system clock note 1: bit resets to ? 0 ? with two-speed start-up mode, and lp, xt, or hs selected as the oscillator mode. bit 2 iofs: intosc frequency stable bit 1 = frequency is stable 0 = frequency is not stable bit 1-0 scs<1:0>: oscillator mode select bits 00 = oscillator mode defined by f osc <2:0> 01 = t1osc is used for system clock 10 = internal rc is used for system clock 11 = reserved legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 41 pic16f87/88 figure 4-6: pic16f87 /88 clock diagram 4.6.4 modifying the ircf bits the ircf bits can be modified at any time, regardless of which clock source is currently being used as the sys- tem clock. the internal oscillator allows users to change the frequency during run time. this is achieved by mod- ifying the ircf bits in the osccon register. the sequence of events that occur after the ircf bits are modified is dependent upon the initial value of the ircf bits before they are modified. if the intrc (31.25 khz, ircf<2:0> = 000 ) is running and the ircf bits are modified to any other value than ? 000 ?, a 4 ms clock switch delay is turned on. code execution continues at a higher than expected frequency while the new fre- quency stabilizes. time sensitive code should wait for the iofs bit in the osccon register to become set before continuing. this bit can be monitored to ensure that the frequency is stable before using the system clock in time critical applications. if the ircf bits are modified while the internal oscillator is running at any other frequency than intrc (31.25 khz ircf<2:0> 000 ), there is no need for a 4 ms clock switch delay. the new intosc frequency will be stable immediately after the eight falling edges. the iofs bit will remain set after clock switching occurs. 4.6.5 clock transition sequence following are three different sequences for switching the internal rc oscillator frequency. clock before switch: 31.25 khz (ircf<2:0> = 000 ) 1. ircf bits are modified to an intosc/intosc postscaler frequency. 2. the clock switching circuitry waits for a falling edge of the current clock, at which point clko is held low. 3. the clock switching circuitry then waits for eight falling edges of requested clock, after which it switches clko to this new clock source. 4. the iofs bit is clear to indicate that the clock is unstable and a 4 ms delay is started. time dependent code should wait for iofs to become set. 5. switchover is complete. clock before switch: one of intosc/intosc postscaler (ircf<2:0> 000 ) 1. ircf bits are modified to intrc (ircf<2:0> = 000 ). 2. the clock switching circuitry waits for a falling edge of the current clock, at which point clko is held low. 3. the clock switching circuitry then waits for eight falling edges of requested clock, after which it switches clko to this new clock source. 4. oscillator switchover is complete. secondary oscillator t1oscen enable oscillator t1oso t1osi osc1 osc2 sleep primary oscillator lp, xt, hs, rc, ec t1osc cpu peripherals postscaler mux mux 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz osccon<6:4> 111 110 101 100 011 010 001 000 31.25 khz 31.25 khz source internal oscillator block wdt, fscm 31.25 khz 8 mhz internal oscillator (intrc) (intosc) config1(f osc 2:f osc 0) scs<1:0>(t1osc) to ti m e r 1 note: caution must be taken when modifying the ircf bits using bcf or bsf instructions. it is possible to modify the ircf bits to a fre- quency that may be out of the v dd specifi- cation range; for example, v dd = 2.0v and ircf = 111 (8 mhz).
pic16f87/88 ds30487b-page 42 preliminary ? 2003 microchip technology inc. clock before switch: one of intosc/intosc postscaler (ircf<2:0> 000 ) 1. ircf bits are modified to a different intosc/ intosc postscaler frequency. 2. the clock switching circuitry waits for a falling edge of the current clock, at which point clko is held low. 3. the clock switching circuitry then waits for eight falling edges of requested clock, after which it switches clko to this new clock source. 4. the iofs bit is set. 5. oscillator switchover is complete. 4.6.6 oscillator delay upon power-up, wake-up and clock switching table 4-3 shows the different delays invoked for vari- ous clock switching sequences. it also shows the delays invoked for por and wake-up. table 4-3: oscillator delay examples switch from switch to frequency oscillator delay comments sleep/por intrc t1osc intosc/ intosc postscaler 31.25 khz 32.768 khz 125khz - 8mhz 5 s - 10 s (approx.) cpu start-up (1) following a wake-up from sleep mode or por, cpu start-up is invoked to allow the cpu to become ready for code execution. intrc/sleep ec, rc dc - 20 mhz intrc (31.25 khz) ec, rc dc - 20 mhz sleep lp, xt, hs 32.768 khz - 20 mhz 1024 clock cycles (ost) following a change from intrc, an ost of 1024 cycles must occur. intrc (31.25 khz) intosc/ intosc postscaler 125khz - 8mhz 4ms refer to section 4.6.4 ?modifying the ircf bits? for further details. note 1: the 5 s-10 s start-up delay is based on a 1 mhz system clock.
? 2003 microchip technology inc. preliminary ds30487b-page 43 pic16f87/88 4.7 power managed modes 4.7.1 rc_run mode when scs bits are configured to run from the intrc, a clock transition is generated if the system clock is not already using the intrc. the event will clear the osts bit, switch the system clock from the primary system clock (if scs<1:0> = 00 ) determined by the value contained in the configuration bits, or from the t1osc (if scs<1:0> = 01 ) to the intrc clock option, and shut down the primary system clock to conserve power. clock switching will not occur if the primary system clock is already configured as intrc. if the system clock does not come from the intrc (31.25 khz) when the scs bits are changed, and the ircf bits in the osccon register are configured for a frequency other than intrc, the frequency may not be stable immediately. the iofs bit (osccon<2>) will be set when the intosc or postscaler frequency is stable, after approximately 4 ms. after a clock switch has been executed, the osts bit is cleared, indicating a low-power mode, and the device does not run from the primary system clock. the internal q clocks are held in the q1 state until eight falling edge clocks are counted on the intrc oscillator. after the eight clock periods have tran- spired, the clock input to the q clocks is released and operation resumes (see figure 4-7). figure 4-7: timing diagram for xt, hs, lp, ec and extrc to rc_run mode q4 q3 q2 osc1 scs<1:0> program pc + 1 pc note 1: t inp =32 s typical. 2: t osc = 50 ns minimum. 3: t scs =8 t inp . 4: t dly =1 t inp . q1 intosc q1 t scs (3) counter q1 t dly (4) t inp (1) system clock t osc (2) q3 q2 q4 q1 q2 pc + 2 pc + 3 q3 q4 q1
pic16f87/88 ds30487b-page 44 preliminary ? 2003 microchip technology inc. 4.7.2 sec_run mode the core and peripherals can be configured to be clocked by t1osc using a 32.768 khz crystal. the crystal must be connected to the t1oso and t1osi pins. this is the same configuration as the low-power timer circuit (see section 7.6 ?timer1 oscillator? ). when scs bits are configured to run from t1osc, a clock transition is generated. it will clear the osts bit, switch the system clock from either the primary system clock, or intrc, depending on the value of scs<1:0> and f osc <2:0>, to the external low-power timer1 oscillator input (t1osc), and shut down the primary system clock to conserve power. after a clock switch has been executed, the internal q clocks are held in the q1 state until eight falling edge clocks are counted on the t1osc. after the eight clock periods have transpired, the clock input to the q clocks is released and operation resumes (see figure 4-8). in addition, t1run (in t1con) is set to indicate that t1osc is being used as the system clock. figure 4-8: timing diagram fo r switching to sec_run mode note 1: the t1oscen bit must be enabled and it is the user?s responsibility to ensure t1osc is stable before clock switching to the t1osc input clock can occur. 2: when t1oscen = 0 , the following possible effects result. original scs<1:0> modified scs<1:0> final scs<1:0> 00 01 00 - no change 00 11 10 - intrc 10 11 10 - no change 10 01 00 - osc defined by f osc <2:0> a clock switching event will occur if the final state of the scs bits is different from the original. q4 q3 q2 osc1 scs<1:0> program pc +1 pc note 1: t t 1 p = 30.52 s. 2: t osc = 50 ns minimum. 3: t scs = 8 t t 1 p 4: t dly = 1 t t 1 p . q1 t1osi q1 t scs (3) counter q1 t dly (4) t t 1 p (1) system clock t osc (2) q3 q2 q4 q1 q2 pc + 2 pc +3 q3 q4 q1
? 2003 microchip technology inc. preliminary ds30487b-page 45 pic16f87/88 4.7.3 sec_run/rc_run to primary clock source when switching from a sec_run or rc_run mode back to the primary system clock, following a change of scs<1:0> to ? 00 ?, the sequence of events that take place will depend upon the value of the f osc bits in the configuration register. if the primary clock source is configured as a crystal (hs, xt, or lp), then the transition will take place after 1024 clock cycles. this is necessary because the crystal oscillator had been powered down until the time of the transition. in order to provide the system with a reliable clock when the changeover has occurred, the clock will not be released to the changeover circuit until the 1024 count has expired. during the oscillator start-up time, the system clock comes from the current system clock. instruction exe- cution and/or peripheral operation continues using the currently selected oscillator as the cpu clock source, until the necessary clock count has expired to ensure that the primary system clock is stable. to know when the ost has expired, the osts bit should be monitored. osts = 1 indicates that the oscillator start-up timer has timed out and the system clock comes from the primary clock source. following the oscillator start-up time, the internal q clocks are held in the q1 state until eight falling edge clocks are counted from the primary system clock. the clock input to the q clocks is then released, and oper- ation resumes with primary system clock determined by the f osc bits (see figure 4-10). when in sec_run mode, the act of clearing the t1oscen bit in the t1con register will cause scs<0> to be cleared, which causes the scs<1:0> bits to revert to ? 00 ? or ? 10 ?, depending on what scs<1> is. although the t1oscen bit was cleared, t1osc will be enabled and instruction execution will continue until the ost time-out for the main system clock is com- plete. at that time, the system clock will switch from the t1osc to the primary clock or the intrc. following this, the t1 oscillator will be shut down. 4.7.3.1 returning to primary clock source sequence changing back to the primary oscillator from sec_run or rc_run can be accomplished by either changing scs<1:0> to ? 00 ?, or clearing the t1oscen bit in the t1con register (if t1osc was the secondary clock). the sequence of events that follows is the same for both modes: 1. if the primary system clock is configured as ec, rc, or intrc, then the ost time-out is skipped. skip to step 3. 2. if the primary system clock is configured as an external oscillator (hs, xt, lp), then the ost will be active, waiting for 1024 clocks of the primary system clock. 3. on the following q1, the device holds the system clock in q1. 4. the device stays in q1 while eight falling edges of the primary system clock are counted. 5. once the eight counts transpire, the device begins to run from the primary oscillator. 6. if the secondary clock was intrc and the pri- mary is not intrc, the intrc will be shut down to save current, providing that the intrc is not being used for any other function, such as wdt, or fail-safe clock monitoring. 7. if the secondary clock was t1osc, the t1osc will continue to run if t1oscen is still set, otherwise the t1 oscillator will be shut down. note: if the primary system clock is either rc or ec, an internal delay timer (5-10 s) will suspend operation after exiting secondary clock mode to allow the cpu to become ready for code execution.
pic16f87/88 ds30487b-page 46 preliminary ? 2003 microchip technology inc. figure 4-9: timing for transition between sec_run/rc_run and primary clock q4 q1 q3 q4 osc1 program pc pc + 1 sec. osc primary clock t ost q1 pc +3 t osc (3) t dly (5) t t 1 p (1) or t inp (2) t scs (4) q2 osc2 q3 q4 q1 osts system clock pc + 2 counter q2 q2 q3 q4 scs<1:0> note 1: t t 1 p = 30.52 s. 2: t inp = 32 s typical. 3: t osc = 50 ns minimum. 4: t scs = 8 t inp or 8t t 1 p . 5: t dly = 1 t inp or 1t t 1 p .
? 2003 microchip technology inc. preliminary ds30487b-page 47 pic16f87/88 4.7.3.2 returning to primary oscillator with a reset a reset will clear scs<1:0> back to ? 00 ?. the sequence for starting the primary oscillator following a reset is the same for all forms of reset, including por. there is no transition sequence from the alternate system clock to the primary system clock on a reset condition. instead, the device will reset the state of the osccon register and default to the primary system clock. the sequence of events that take place after this will depend upon the value of the f osc bits in the configuration register. if the external oscillator is configured as a crystal (hs, xt, or lp), the cpu will be held in the q1 state until 1024 clock cycles have transpired on the primary clock. this is necessary because the crystal oscillator had been powered down until the time of the transition. during the oscillator start-up time, instruction execution and/or peripheral operation is suspended. if the primary system clock is either rc, ec, or intrc, the cpu will begin operating on the first q1 cycle following the wake-up event. this means that there is no oscillator start-up time required because the primary clock is already stable; however, there is a delay between the wake-up event and the following q2. an internal delay timer of 5-10 s will suspend operation after the reset to allow the cpu to become ready for code execution. the cpu and peripheral clock will be held in the first q1. the sequence of events is as follows: 1. a device reset is asserted from one of many sources (wdt, bor, mclr , etc.). 2. the device resets and the cpu start-up timer is enabled if in sleep mode. the device is held in reset until the cpu start-up time-out is complete. 3. if the primary system clock is configured as an external oscillator (hs, xt, lp), then the ost will be active waiting for 1024 clocks of the pri- mary system clock. while waiting for the ost, the device will be held in reset. the ost and cpu start-up timers run in parallel. 4. after both the cpu start-up and ost timers have timed out, the device will wait for one addi- tional clock cycle and instruction execution will begin. figure 4-10: primary system clock after reset (hs, xt, lp) note: if two-speed clock start-up mode is enabled, the intrc will act as the system clock until the ost timer has timed out. q4 q1 q3 q4 q1 q2 osc1 peripheral sleep program pc 0000h t1osi t ost q3 t osc (2) t t 1 p (1) q4 osc2 osts system clock 0001h q1 q2 q3 q4 q1 q2 clock counter 0004h 0005h 0003h q1 q2 q3 q4 reset t cpu (3) note 1: t t 1 p = 30.52 s. 2: t osc = 50 ns minimum. 3: t cpu = 5-10 s (1 mhz system clock). cpu start-up
pic16f87/88 ds30487b-page 48 preliminary ? 2003 microchip technology inc. figure 4-11: primary system clock after reset (ec, rc, intrc) q4 q1 q3 q4 q1 q2 osc1 program pc 0000h t1osi q3 t t 1 p (1) q4 osc2 osts system clock 0001h q1 q2 q3 q4 q1 q2 counter 0003h 0004h 0002h q1 q2 q3 q4 mclr t cpu (2) note 1: t t 1 p = 30.52 s. 2: t cpu = 5 - 10 s (1 mhz system clock). cpu start-up
? 2003 microchip technology inc. preliminary ds30487b-page 49 pic16f87/88 table 4-4: clock switching modes current system clock scs bits <1:0> modified to: delay osts bit iofs bit t1run bit new system clock comments lp, xt, hs, t1osc, ec, rc 10 (intrc) f osc <2:0> = lp, xt or hs 8 clocks of intrc 01 (1) 0 intrc or intosc or intosc postscaler the internal rc oscillator frequency is dependant upon the ircf bits. lp, xt, hs, intrc, ec, rc 01 (t1osc) f osc <2:0> = lp, xt or hs 8 clocks of t1osc 0 n/a 1 t1osc t1oscen bit must be enabled. intrc t1osc 00 f osc <2:0> = ec or f osc <2:0> = rc 8 clocks of ec or rc 1 n/a 0 ec or rc intrc t1osc 00 f osc <2:0> = lp, xt, hs 1024 clocks (ost) + 8 clocks of lp, xt, hs 1 n/a 0 lp, xt, hs during the 1024 clocks, program execution is clocked from the second- ary oscillator until the primary oscillator becomes stable. lp, xt, hs 00 (due to reset) lp, xt, hs 1024 clocks (ost) 1 n/a 0 lp, xt, hs when a reset occurs, there is no clock transition sequence. instruction execution and/or peripheral opera- tion is suspended unless two-speed start-up mode is enabled, after which the intrc will act as the system clock until the ost timer has expired. note 1: if the new clock source is intosc or intosc postscale r, then the iofs bit will be set 4 ms after the clock change.
pic16f87/88 ds30487b-page 50 preliminary ? 2003 microchip technology inc. 4.7.4 exiting sleep with an interrupt any interrupt, such as wdt or int0, will cause the part to leave the sleep mode. the scs bits are unaffected by a sleep command and are the same before and after entering and leaving sleep. the clock source used after an exit from sleep is determined by the scs bits. 4.7.4.1 sequence of events if scs<1:0> = 00 : 1. the device is held in sleep until the cpu start-up time-out is complete. 2. if the primary system clock is configured as an external oscillator (hs, xt, lp), then the ost will be active waiting for 1024 clocks of the primary system clock. while waiting for the ost, the device will be held in sleep unless two-speed start-up is enabled. the ost and cpu start-up timers run in parallel. refer to section 15.12.3 ?two-speed clock start-up mode? for details on two-speed start-up. 3. after both the cpu start-up and ost timers have timed out, the device will exit sleep and begin instruction execution with the primary clock defined by the f osc bits. if scs<1:0> = 01 or 10 : 1. the device is held in sleep until the cpu start-up time-out is complete. 2. after the cpu start-up timer has timed out, the device will exit sleep and begin instruction execution with the selected oscillator mode. note: if a user changes scs<1:0> just before entering sleep mode, the system clock used when exiting sleep mode could be different than the system clock used when entering sleep mode. as an example, if scs<1:0> = 01 and t1osc is the system clock, and the following instructions are executed: bcf osccon,scs0 sleep then a clock change event is executed. if the primary oscillator is xt, lp, or hs, the core will continue to run off t1osc and execute the sleep command. when sleep is exited, the part will resume operation with the primary oscillator after the ost has expired.
? 2003 microchip technology inc. preliminary ds30487b-page 51 pic16f87/88 5.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro ? mid-range reference manual (ds33023). 5.1 porta and the trisa register porta is a 8-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register, reads the status of the pins, whereas writing to it, will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input and with analog input to become the ra4/an4/ t0cki/c2out pin. the ra4/an4/t0cki/c2out pin is a schmitt trigger input and full cmos output driver. pin ra5 is multiplexed with the master clear module input. the ra5/mclr /v pp pin is a schmitt trigger input. pin ra6 is multiplexed with the oscillator module input and external oscillator output. pin ra7 is multiplexed with the oscillator module input and external oscillator input. pin ra6/osc2/clko and pin ra7/osc1/clki are schmitt trigger inputs and full cmos output drivers. pins ra<1:0> are multiplexed with analog inputs. pins ra<3:2> are multiplexed with analog inputs, compara- tor outputs, and v ref inputs. pins ra<3:0> have ttl inputs and full cmos output drivers. example 5-1: initializing porta table 5-1: porta functions note: on a power-on reset, the pins porta<4:0> are configured as analog inputs and read as ? 0 ?. banksel porta ; select bank of porta clrf porta ; initialize porta by ; clearing output ; data latches banksel ansel ; select bank of ansel movlw 0x00 ; configure all pins movwf ansel ; as digital inputs movlw 0xff ; value used to ; initialize data ; direction movwf trisa ; set ra<7:0> as inputs name bit# buffer function ra0/an0 bit 0 ttl input/output or analog input. ra1/an1 bit 1 ttl input/output or analog input. ra2/an2/cv ref /v ref - (2) bit 2 ttl input/output or analog input or v ref- or comparator v ref output. ra3/an3/v ref + (2) /c1out bit 3 ttl input/output or analog input or v ref+ or comparator output. ra4/an4 (2) /t0cki/c2out bit 4 st input/output, analog input or tmr0 external input or comparator output. ra5/mclr /v pp bit 5 st input, master clear (reset) or programming voltage input. ra6/osc2/clko bit 6 st input/output, connects to crystal or resonator, oscillator output or 1/4 the frequency of osc1, and denotes the instruction cycle in rc mode. ra7/osc1/clki bit 7 st/cmos (1) input/output, connects to crystal or resonator or oscillator input. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise. 2: pic16f88 only.
pic16f87/88 ds30487b-page 52 preliminary ? 2003 microchip technology inc. table 5-2: summary of registers associated with porta figure 5-1: block diagram of ra0/an0:ra1/an1 pins address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0000 (1) xxx0 0000 (2) uuuu 0000 (1) uuu0 0000 (2) 85h trisa trisa7 trisa6 trisa5 (3) porta data direction register 1111 1111 1111 1111 9fh adcon1 adfm adcs2 vcfg1 vcfg0 ? ? ? ? 0000 ---- 0000 ---- 9bh ansel (4) ? ans6 ans5 ans4 ans3 ans2 ans1 ans0 -111 1111 -111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. note 1: this value applies only to the pic16f87. 2: this value applies only to the pic16f88. 3: pin 5 is an input only; the state of the tr isa5 bit has no effect and will always read ? 1 ?. 4: pic16f88 device only. data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog v ss v dd i/o pin q d q ck input mode d q en to comparator ttl input buffer v dd to a/d module channel input (pic16f88 only)
? 2003 microchip technology inc. preliminary ds30487b-page 53 pic16f87/88 figure 5-2: block di agram of ra3/an3/v ref +/c1out pin figure 5-3: block di agram of ra2/an2/cv ref /v ref - pin data bus q d q ck n wr porta wr trisa data latch tris latch rd trisa rd porta v ss ra3 pin q d q ck d q en to a/d module channel input (pic16f88 only) comparator 1 output comparator mode = 110 v dd analog input mode to a/d module channel v ref + input (pic16f88 only) p v dd to comparator v ss input buffer ttl data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog v ss v dd ra2 pin q d q ck d q en to comparator ttl input buffer input mode v dd to a/d module channel input (pic16f88 only) cvroe cv ref to a/d module v ref - (pic16f88 only)
pic16f87/88 ds30487b-page 54 preliminary ? 2003 microchip technology inc. figure 5-4: block diagram of ra4/an4/t0cki/c2out pin figure 5-5: block diagram of ra5/mclr /v pp pin data bus q d q ck n wr porta wr trisa data latch tris latch rd trisa rd porta v ss ra4 pin d q en tmr0 clock input schmitt trigger input buffer comparator 2 output comparator mode = 011 , 101 , 110 1 0 v dd analog input mode to a/d module channel input (pic16f88 only) p v dd q d q ck d q en mclr filter ra5/mclr /v pp pin rd port mclr circuit mclre mclre data bus rd tris schmitt trigger buffer v ss v ss schmitt trigger input buffer
? 2003 microchip technology inc. preliminary ds30487b-page 55 pic16f87/88 figure 5-6: block diagra m of ra6/osc2/clko pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta v ss v dd ra6/osc2/clko pin q d q ck d q en oscillator circuit from osc1 (f osc = 1x0 , 011 ) p n v ss v dd clko (f osc /4) v dd note 1: i/o pins have protection diodes to v dd and v ss . 2: clko signal is 1/4 of the f osc frequency. (f osc = 1x0 , 011 ) (f osc = 1x1 ) v ss schmitt trigger input buffer
pic16f87/88 ds30487b-page 56 preliminary ? 2003 microchip technology inc. figure 5-7: block diagra m of ra7/osc1/clki pin data bus q d q ck wr porta wr trisa data latch tris latch rd trisa rd porta d q en oscillator circuit ra7/osc1/clki pin (1) p n v ss v dd f osc = 10x v dd note 1: i/o pins have protection diodes to v dd and v ss . (f osc = 011 ) f osc = 10x from osc2 v ss schmitt trigger input buffer q d q ck
? 2003 microchip technology inc. preliminary ds30487b-page 57 pic16f87/88 5.2 portb and the trisb register portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of portb?s pins, rb7:rb4, have an interrupt-on- change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are or?d together to generate the rb port change interrupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. rb0/int is an external interrupt input pin and is configured using the intedg bit (option<6>). portb is multiplexed with several peripheral functions (see table 5-3). portb pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portb pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisb as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings.
pic16f87/88 ds30487b-page 58 preliminary ? 2003 microchip technology inc. table 5-3: portb functions table 5-4: summary of registers associated with portb name bit# buffer function rb0/int/ccp1 bit 0 ttl/st (1) input/output pin or external interrupt input. capture input/compare output/pwm output pin. internal software programmable weak pull-up. rb1/sdi/sda bit 1 ttl/st (5) input/output pin, spi data input pin or i 2 c data i/o pin. internal software programmable weak pull-up. rb2/sdo/rx/dt bit 2 ttl/st (4) input/output pin, spi data output pin. usart asynchronous receive or synchronous data. internal software programmable weak pull-up. rb3/pgm/ccp1 (3) bit 3 ttl/st (2) input/output pin, programming in lvp mode or capture input/compare output/pwm output pin. internal software programmable weak pull-up. rb4/sck/scl bit 4 ttl/st (5) input/output pin or spi and i 2 c clock pin (with interrupt-on-change). internal software programmable weak pull-up. rb5/ss /tx/ck bit 5 ttl input/output pin or spi slave select pin (with interrupt-on-change). usart asynchronous transmit or synchronous clock. internal software programmable weak pull-up. rb6/an5/pgc/t1oso/ t1cki bit 6 ttl/st (2) input/output pin, analog input (6) , serial programming clock (with interrupt-on-change), timer1 oscillator output pin or timer1 clock input pin. internal software programmable weak pull-up. rb7/an6/pgd/t1osi bit 7 ttl/st (2) input/output pin, analog input (6) , serial programming data (with interrupt-on-change) or timer1 oscillator input pin. internal software programmable weak pull-up. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: low-voltage icsp programming (lvp) is enabled by default, which disables the rb3 i/o function. lvp must be disabled to enable rb3 as an i/o pin and allow maximum compatibility to the other 18-pin mid-range devices. 4: this buffer is a schmitt trigger input when configured for ccp or ssp mode. 5: this buffer is a schmitt trigger input when configured for spi or i 2 c mode. 6: pic16f88 only. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 9bh ansel (1) ? ans6 ans5 ans4 ans3 ans2 ans1 ans0 -111 1111 -111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb. note 1: pic16f88 device only.
? 2003 microchip technology inc. preliminary ds30487b-page 59 pic16f87/88 figure 5-8: block diagram of rb0 pin note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. data latch rbpu (2) p v dd q d ck q d ck q d en data bus wr portb wr trisb rd trisb rd portb weak pull-up rd portb i/o pin (1) ttl input buffer tris latch 0 1 ccp ccp1 = 1000 , 1001 , 11xx and ccpmx = 1 to int0 or ccp ccp1 = 000
pic16f87/88 ds30487b-page 60 preliminary ? 2003 microchip technology inc. figure 5-9: block diagram of rb1 pin data latch rbpu (2) p v dd q d ck q d ck q d en data bus wr wr rd trisb rd portb weak pull-up rd portb sda (3) i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. 3: the sda schmitt conforms to the i 2 c specification. 1 0 sda output p n v ss v dd q sda drive port /sspen select i 2 c? mode sdi portb trisb
? 2003 microchip technology inc. preliminary ds30487b-page 61 pic16f87/88 figure 5-10: block diagram of rb2 pin dt sdo data latch rbpu (2) p v dd q d ck q d ck q d en data bus wr portb wr trisb rd trisb rd portb weak pull-up rd portb rx/dt i/o pin (1) ttl input buffer schmitt trigger buffer tris latch 1 0 p n v ss v dd q dt drive spen 1 0 sspen note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. sspen + spen
pic16f87/88 ds30487b-page 62 preliminary ? 2003 microchip technology inc. figure 5-11: block diagram of rb3 pin data latch rbpu (2) p v dd q d ck q d ck q d en data bus wr wr rd trisb rd portb weak pull-up rd portb i/o pin (1) ttl input buffer tris latch portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. 0 1 ccp to pgm or ccp ccp1 = 1000 , 1001 , 11xx and ccpmx = 0 ccp1 = 0100 , 0101 , 0110 , 0111 and ccpmx = 0 or lvp = 1 trisb
? 2003 microchip technology inc. preliminary ds30487b-page 63 pic16f87/88 figure 5-12: block diagram of rb4 pin data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr wr set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch ttl input buffer q3 q1 portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. 3: the scl schmitt conforms to the i 2 c? specification. sck sck/scl 1 0 port /sspen scl (3) p n v ss v dd scl drive trisb
pic16f87/88 ds30487b-page 64 preliminary ? 2003 microchip technology inc. figure 5-13: block diagram of rb5 pin data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr wr set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch q3 q1 portb ss /tx/ck port /sspen note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. trisb ttl input buffer
? 2003 microchip technology inc. preliminary ds30487b-page 65 pic16f87/88 figure 5-14: block diagram of rb6 pin data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr portb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch q3 q1 note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. pgc/t1cki analog ttl input buffer input mode t1oscen/icd/prog from t1osco output to a/d module channel input (pic16f88 only) analog input mode mode
pic16f87/88 ds30487b-page 66 preliminary ? 2003 microchip technology inc. figure 5-15: block diagram of rb7 pin data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr t1oscen set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch q3 q1 portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. pgd pgd port /program mode/icd analog ttl input buffer input mode to t1osci input 1 0 pgd drven t1oscen wr trisb to a/d module channel input (pic16f88 only) 1 0 analog input mode
? 2003 microchip technology inc. preliminary ds30487b-page 67 pic16f87/88 6.0 timer0 module the timer0 module timer/counter has the following features: 8-bit timer/counter readable and writable 8-bit software programmable prescaler internal or external clock select interrupt on overflow from ffh to 00h edge select for external clock additional information on the timer0 module is available in the picmicro ? mid-range mcu family reference manual (ds33023). figure 6-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. 6.1 timer0 operation timer0 operation is controlled through the option register (see register 2-2). timer mode is selected by clearing bit t0cs (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option<5>). in counter mode, timer0 will increment, either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit, t0se (option<4>). clearing bit t0se selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.3 ?using timer0 with an external clock? . the prescaler is mutually, exclusively shared between the timer0 module and the watchdog timer. the prescaler is not readable or writable. section 6.4 ?prescaler? details the operation of the prescaler. 6.2 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit tmr0if (intcon<2>). the interrupt can be masked by clearing bit tmr0ie (intcon<5>). bit tmr0if must be cleared in software by the timer0 module interrupt service routine before re-enabling this inter- rupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut-off during sleep. figure 6-1: block diagram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clko (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1 mux m u x m u x psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option<5:0>). psa m u x 0 1 0 1 data bus set flag bit tmr0if on overflow 8 psa t0cs prescaler 31.25 khz wdt timer wdt enable bit 16-bit prescaler
pic16f87/88 ds30487b-page 68 preliminary ? 2003 microchip technology inc. 6.3 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki, with the internal phase clocks, is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2 t osc (and a small rc delay of 20 ns) and low for at least 2 t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. 6.4 prescaler there is only one prescaler available, which is mutually exclusively shared between the timer0 module and the watchdog timer. a prescaler assignment for the timer0 module means that the prescaler cannot be used by the watchdog timer, and vice versa. this prescaler is not readable or writable (see figure 6-1). the psa and ps2:ps0 bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. register 6-1: option_reg register (address 81h, 181h) note: although the prescaler can be assigned to either the wdt or timer0, but not both, a new divide counter is implemented in the wdt circuit to give multiple wdt time-out selections. this allows tmr0 and wdt to each have their own scaler. refer to section 15.12 ?watchdog timer (wdt)? for further details. note: writing to tmr0, when the prescaler is assigned to timer0, will clear the prescaler count but will not change the prescaler assignment. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit bit 6 intedg: interrupt edge select bit bit 5 t0cs : tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: to avoid an unintended device reset, the instruction sequence shown in the picmicro ? mid-range mcu family reference manual (ds33023) must be exe- cuted when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
? 2003 microchip technology inc. preliminary ds30487b-page 69 pic16f87/88 example 6-1: changing the prescaler assignment from wdt to timer0 table 6-1: registers associated with timer0 clrwdt ; clear wdt and prescaler banksel option ; select bank of option movlw b'xxxx0xxx' ; select tmr0, new prescale movwf option ; value and clock source address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 01h,101h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 81h,181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by timer0.
pic16f87/88 ds30487b-page 70 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 71 pic16f87/88 7.0 timer1 module the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l), which are readable and writable. the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing tmr1 interrupt enable bit, tmr1ie (pie1<0>). the timer1 oscillator can be used as a secondary clock source in low-power modes. when the t1run bit is set along with scs<1:0> = 01 , the timer1 oscillator is providing the system clock. if the fail-safe clock mon- itor is enabled, and the timer1 oscillator fails while pro- viding the system clock, polling the t1run bit will indicate whether the clock is being provided by the timer1 oscillator or another source. timer1 can also be used to provide real-time clock (rtc) functionality to applications with only a minimal addition of external components and code overhead. 7.1 timer1 operation timer1 can operate in one of three modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. timer1 can be enabled/disabled by setting/clearing control bit, tmr1on (t1con<0>). timer1 also has an internal ?reset input?. this reset can be generated by the ccp1 module as the special event trigger (see section 9.1 ?capture mode? ). register 7-1 shows the timer1 control register. when the timer1 oscillator is enabled (t1oscen is set), the rb6/t1oso/t1cki/pgc and rb7/t1osi/ pgd pins become inputs. that is, the trisb<7:6> value is ignored and these pins read as ? 0 ?. additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023).
pic16f87/88 ds30487b-page 72 preliminary ? 2003 microchip technology inc. register 7-1: t1con: timer1 control regist er (address 10h) u-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 t1run : timer1 system clock status bit 1 = system clock is derived from timer1 oscillator 0 = system clock is derived from another source bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rb6/an5/pgc/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 73 pic16f87/88 7.2 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f osc /4. the synchronize control bit, t1sync (t1con<2>), has no effect since the internal clock is always in sync. 7.3 timer1 counter operation timer1 may operate in asynchronous or synchronous mode, depending on the setting of the tmr1cs bit. when timer1 is being incremented via an external source, increments occur on a rising edge. after timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. 7.4 timer1 operation in synchronized counter mode counter mode is selected by setting bit tmr1cs. in this mode, the timer increments on every rising edge of clock input on pin rb7/an6/pgd/t1osi, when bit t1oscen is set, or on pin rb6/an5/pgc/t1oso/ t1cki, when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the prescaler stage is an asynchronous ripple counter. in this configuration, during sleep mode, timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. the prescaler, however, will continue to increment. figure 7-1: timer1 incrementing edge figure 7-2: timer1 block diagram t1cki (default high) t1cki (default low) note: arrows indicate counter increments. tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 q clock t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1osi t1oso/t1cki note 1: when the t1oscen bit is cleared, the inverter is turned off. this e liminates power drain. set flag bit tmr1if on overflow tmr1
pic16f87/88 ds30487b-page 74 preliminary ? 2003 microchip technology inc. 7.5 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow that will wake-up the processor. however, special precautions in software are needed to read/write the timer ( section 7.5.1 ?reading and writing timer1 in asynchronous counter mode? ). in asynchronous counter mode, timer1 cannot be used as a time base for capture or compare operations. 7.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. the example codes provided in example 7-1 and example 7-2 demonstrate how to write to and read timer1 while it is running in asynchronous mode. example 7-1: writing a 16-bit free-running timer example 7-2: reading a 16-bit free-running timer ; all interrupts are disabled clrf tmr1l ; clear low byte, ensures no rollover into tmr1h movlw hi_byte ; value to load into tmr1h movwf tmr1h, f ; write high byte movlw lo_byte ; value to load into tmr1l movwf tmr1h, f ; write low byte ; re-enable the interrupt (if required) continue ; continue with your code ; all interrupts are disabled movf tmr1h, w ; read high byte movwf tmph movf tmr1l, w ; read low byte movwf tmpl movf tmr1h, w ; read high byte subwf tmph, w ; sub 1st read with 2nd read btfsc status,z ; is result = 0 goto continue ; good 16-bit read ; tmr1l may have rolled over between the read of the high and low bytes. ; reading the high and low bytes now will read a good value. movf tmr1h, w ; read high byte movwf tmph movf tmr1l, w ; read low byte movwf tmpl ; re-enable the interrupt (if required) continue ; continue with your code
? 2003 microchip technology inc. preliminary ds30487b-page 75 pic16f87/88 7.6 timer1 oscillator a crystal oscillator circuit is built between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low-power oscillator rated up to 32.768 khz. it will continue to run during all power managed modes. it is primarily intended for a 32 khz crystal. the circuit for a typical lp oscillator is shown in figure 7-3. table 7-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper oscillator start-up. figure 7-3: external components for the timer1 lp oscillator table 7-1: capacitor selection for the timer1 oscillator 7.7 timer1 oscillator layout considerations the timer1 oscillator circuit draws very little power dur- ing operation. due to the low-power nature of the oscil- lator, it may also be sensitive to rapidly changing signals in close proximity. the oscillator circuit, shown in figure 7-3, should be located as close as possible to the microcontroller. there should be no circuits passing within the oscillator circuit boundaries other than v ss or v dd . if a high-speed circuit must be located near the oscilla- tor, a grounded guard ring around the oscillator circuit, as shown in figure 7-4, may be helpful when used on a single-sided pcb, or in addition to a ground plane. figure 7-4: oscillator circuit with grounded guard ring 7.8 resetting timer1 using a ccp trigger output if the ccp1 module is configured in compare mode to generate a ?special event trigger" signal (ccp1m3:ccp1m0 = 1011) , the signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l regis- ter pair effectively becomes the period register for timer1. osc type freq c1 c2 lp 32 khz 33 pf 33 pf note 1: microchip suggests this value as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. pic16f87/88 t1osi t1oso c2 33 pf c1 33 pf xtal 32.768 khz note: see the notes with table 7-1 for additional information about capacitor selection. note: the special event triggers from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). osc1 v ss osc2 rb7 rb6 rb5
pic16f87/88 ds30487b-page 76 preliminary ? 2003 microchip technology inc. 7.9 resetting timer1 register pair (tmr1h, tmr1l) tmr1h and tmr1l registers are not reset to 00h on a por, or any other reset, except by the ccp1 special event triggers. t1con register is reset to 00h on a power-on reset or a brown-out reset, which shuts off the timer and leaves a 1:1 prescale. in all other resets, the register is unaffected. 7.10 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. 7.11 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 7.6 ?timer1 oscillator? , above), gives users the option to include rtc function- ality to their applications. this is accomplished with an inexpensive watch crystal to provide an accurate time base, and several lines of application code to calculate the time. when operating in sleep mode and using a battery or super capacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 7-3, demonstrates a simple method to incre- ment a counter at one-second intervals using an inter- rupt service routine. incrementing the tmr1 register pair to overflow triggers the interrupt and calls the rou- tine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. since the register pair is 16-bits wide, counting up to overflow the register directly from a 32.768 khz clock would take 2 seconds. to force the overflow at the required one-second intervals, it is necessary to pre- load it; the simplest method is to set the msbit of tmr1h with a bsf instruction. note that the tmr1l register is never pre-loaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode, and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ), as shown in the rou- tine, rtcinit . the timer1 oscillator must also be enabled and running at all times.
? 2003 microchip technology inc. preliminary ds30487b-page 77 pic16f87/88 example 7-3: implementing a real-time clock using a timer1 interrupt service table 7-2: registers associated with timer1 as a timer/counter rtcinit banksel tmr1h movlw 0x80 ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b?00001111? ; configure for external clock, movwf t1con ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins movlw .12 movwf hours banksel pie1 bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr banksel tmr1h bsf tmr1h,7 ; preload for 1 sec overflow bcf pir1,tmr1if ; clear interrupt flag incf secs,f ; increment seconds movf secs,w sublw .60 btfss status,z ; 60 seconds elapsed? return ; no, done clrf seconds ; clear seconds incf mins,f ; increment minutes movf mins,w sublw .60 btfss status,z ; 60 seconds elapsed? return ; no, done clrf mins ; clear minutes incf hours,f ; increment hours movf hours,w sublw .24 btfss status,z ; 24 hours elapsed? return ; no, done clrf hours ; clear hours return ; done address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on -000 0000 -uuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module.
pic16f87/88 ds30487b-page 78 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 79 pic16f87/88 8.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it can be used as the pwm time base for the pwm mode of the ccp1 module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if (pir1<1>)). timer2 can be shut-off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. register 8-1 shows the timer2 control register. additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023). 8.1 timer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr , wdt reset, or brown-out reset) tmr2 is not cleared when t2con is written. 8.2 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module, which optionally uses it to generate a shift clock. figure 8-1: timer2 block diagram comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to
pic16f87/88 ds30487b-page 80 preliminary ? 2003 microchip technology inc. register 8-1: t2con: timer2 control regist er (address 12h) table 8-1: registers associated with timer2 as a timer/counter u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps<3:0>: timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale 1111 = 1:16 postscale bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 11h tmr2 timer2 module register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module.
? 2003 microchip technology inc. preliminary ds30487b-page 81 pic16f87/88 9.0 capture/compare/pwm (ccp) module the capture/compare/pwm (ccp) module contains a 16-bit register that can operate as a: 16-bit capture register 16-bit compare register pwm master/slave duty cycle register. table 9-1 shows the timer resources of the ccp module modes. capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. the special event trigger is generated by a compare match which will reset timer1 and start an a/d conversion (if the a/d module is enabled). the ccp module?s input/output pin (ccp1) can be configured as rb0 or rb3. this selection is set in bit 12 (ccpmx) of the configuration word. additional information on the ccp module is available in the picmicro ? mid-range mcu reference manual , (ds33023) and in application note an594, ? using the ccp modules ? (ds00594). table 9-1: ccp mode - timer resource register 9-1: ccp1con: capture/compare/pwm control register 1 (address 17h) ccp mode timer resource capture compare pwm timer1 timer1 timer2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 ccp1x:ccp1y: pwm least significant bits capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccp1m<3:0>: ccp1 mode select bits 0000 = capture/compare/pwm disabled (resets ccp1 module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccp1if bit is set) 1001 = compare mode, clear output on match (ccp1if bit is set) 1010 = compare mode, generate software interrupt on match (ccp1if bit is set, ccp1 pin is unaffected) 1011 = compare mode, trigger special event (ccp1if bit is set, ccp1 pin is unaffected); ccp1 resets tmr1 and starts an a/d conversion (if a/d module is enabled) 11xx =pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 82 preliminary ? 2003 microchip technology inc. 9.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on ccp1 pin. an event is defined as: every falling edge every rising edge every 4th rising edge every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit, ccp1if (pir1<2>), is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value is overwritten by the new captured value. 9.1.1 ccp pin configuration in capture mode, the ccp1 pin should be configured as an input by setting the trisb bit. figure 9-1: capture mode operation block diagram 9.1.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 9.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit, ccp1if, following any such change in operating mode. 9.1.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 9-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 9-1: changing between capture prescalers note 1: if the ccp1 pin is configured as an output, a write to the port can cause a capture condition. 2: the trisb bit (0 or 3) is dependent upon the setting of configuration bit 12 (ccpmx). ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable q?s ccp1con<3:0> ccp1 pin prescaler 1, 4, 16 and edge detect clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ;the new prescaler ;move value and ccp on movwf ccp1con ;load ccp1con with this ;value
? 2003 microchip technology inc. preliminary ds30487b-page 83 pic16f87/88 9.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the ccp1 pin is: driven high driven low remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt flag bit, ccp1if, is set. figure 9-2: compare mode operation block diagram 9.2.1 ccp pin configuration the user must configure the ccp1 pin as an output by clearing the trisb bit. 9.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 9.2.3 software interrupt mode when generate software interrupt is chosen, the ccp1 pin is not affected. only a ccp interrupt is generated (if enabled). 9.2.4 special event trigger in this mode, an internal hardware trigger is generated that may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair and starts an a/d conversion (if the a/d module is enabled). this allows the ccpr1 regis- ter to effectively be a 16-bit programmable period register for timer1. table 9-2: registers associated with capture, compare and timer1 ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match ccp1 pin trisb ccp1con<3:0> mode select output enable special event trigger will: reset timer1, but not set interrupt flag bit, tmr1if (pir1<0>) set bit go/done (adcon0<2>) bit, which starts an a/d conversion note 1: clearing the ccp1con register will force the ccp1 compare output latch to the default low level. this is not the data latch. 2: the trisb bit (0 or 3) is dependent upon the setting of configuration bit 12 (ccpmx). note: the special event trigger from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 86h trisb portb data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on -000 0000 -uuu uuuu 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by capture and timer1.
pic16f87/88 ds30487b-page 84 preliminary ? 2003 microchip technology inc. 9.3 pwm mode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portb data latch, the trisb bit must be cleared to make the ccp1 pin an output. figure 9-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to setup the ccp module for pwm operation, see section 9.3.3 ?setup for pwm operation? . figure 9-3: simplified pwm block diagram a pwm output (figure 9-4) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 9-4: pwm output 9.3.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula. equation 9-1: pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 9.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time. equation 9-2: ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read only register. the ccpr1h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portb i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisb ccp1 pin note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 8.0 ?timer2 module? ) is not used in the deter- mination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] ? 4 t osc (tmr2 prescale value) pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value)
? 2003 microchip technology inc. preliminary ds30487b-page 85 pic16f87/88 the maximum pwm resolution (bits) for a given pwm frequency is given by the following formula. equation 9-3: 9.3.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisb bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 9-3: example pwm frequencies and resolutions at 20 mhz table 9-4: registers associated with pwm and timer2 note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. log ( f pwm log(2) f osc ) bits = resolution note: the trisb bit (0 or 3) is dependant upon the setting of configuration bit 12 (ccpmx). pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 86h trisb portb data direction register 1111 1111 1111 1111 11h tmr2 timer2 module register 0000 0000 0000 0000 92h pr2 timer2 module period register 1111 1111 1111 1111 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by pwm and timer2.
pic16f87/88 ds30487b-page 86 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 87 pic16f87/88 10.0 synchronous serial port (ssp) module 10.1 ssp module overview the synchronous serial port (ssp) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the ssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) an overview of i 2 c operations and additional informa- tion on the ssp module can be found in the picmicro ? mid-range mcu family reference manual (ds33023). refer to application note an578, ?use of the ssp module in the i 2 c? multi-master environment? (ds00578). 10.2 spi mode this section contains register definitions and operational characteristics of the spi module. spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. to accomplish communication, typically three pins are used: serial data out (sdo) rb2/sdo/rx/dt serial data in (sdi) rb1/sdi/sda serial clock (sck) rb4/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: slave select (ss ) rb5/ss/ tx/ck when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>) and the sspstat register (sspstat<7:6>). these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only)
pic16f87/88 ds30487b-page 88 preliminary ? 2003 microchip technology inc. register 10-1: sspstat: synchronous serial port stat us register (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p (1) s (1) r/w ua bf bit 7 bit 0 bit 7 smp: spi data input sample phase bit spi master mode : 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time (microwire ? ) spi slave mode : this bit must be cleared when spi is used in slave mode. i 2 c mode : this bit must be maintained clear. bit 6 cke: spi clock edge select bit spi mode, ckp = 0 : 1 = data transmitted on rising edge of sck (microwire alternate) 0 = data transmitted on falling edge of sck spi mode, ckp = 1 : 1 = data transmitted on falling edge of sck (microwire alternate) 0 = data transmitted on rising edge of sck i 2 c mode : this bit must be maintained clear. bit 5 d/a : data/address bit (i 2 c mode only) in i 2 c slave mode : 1 = indicates that the last byte received was data 0 = indicates that the last byte received was address bit 4 p: stop bit (1) (i 2 c mode only) 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last bit 3 s: start bit (1) (i 2 c mode only) 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write information bit (i 2 c mode only) holds the r/w bit information following the last address match, and is only valid from address match to the next start bit, stop bit, or ack bit. 1 =read 0 = write bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive (spi and i 2 c modes) : 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (in i 2 c mode only) : 1 = transmit in progress, sspbuf is full (8 bits) 0 = transmit complete, sspbuf is empty note 1: this bit is cleared when the ssp module is disabled (i.e., the sspen bit is cleared). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 89 pic16f87/88 register 10-2: sspcon: synchronous serial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen (1) ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit 1 = an attempt to write the sspbuf register failed because the ssp module is busy (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit in spi mode : 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?don?t care? in transmit mode. sspov must be cleared in software in either mode. 0 = no overflow bit 5 sspen: synchronous serial port enable bit (1) in spi mode : 1 = enables serial port and configures sck, sdo, and sdi as serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode : 1 = enables the serial port and configures the sda and scl pins as serial port pins 0 = disables serial port and configures these pins as i/o port pins note 1: in both modes, when enabled, these pins must be properly configured as input or output. bit 4 ckp: clock polarity select bit in spi mode : 1 = transmit happens on falling edge, receive on rising edge. idle state for clock is a high level. 0 = transmit happens on rising edge, receive on falling edge. idle state for clock is a low level. in i 2 c slave mode : sck release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) bit 3-0 sspm<3:0>: synchronous serial port mode select bits 0000 = spi master mode, clock = osc/4 0001 = spi master mode, clock = osc/16 0010 = spi master mode, clock = osc/64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1011 = i 2 c firmware controlled master mode (slave idle) 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1000 , 1001 , 1010 , 1100 , 1101 = reserved legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 90 preliminary ? 2003 microchip technology inc. figure 10-1: ssp block diagram (spi mode) to enable the serial port, ssp enable bit, sspen (sspcon<5>), must be set. to reset or reconfigure spi mode, clear bit sspen, re-initialize the sspcon register, and then set bit sspen. this configures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the trisb register) appropriately programmed. that is: sdi must have trisb<1> set sdo must have trisb<2> cleared sck (master mode) must have trisb<4> cleared sck (slave mode) must have trisb<4> set ss must have trisb<5> set table 10-1: registers associated with spi operation read write internal data bus rb1/sdi/sda rb2/sdo/rx/dt rb5/ss / rb4/sck/ sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 trisb<4> 2 edge select 2 4 scl tx/ck note 1: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke = 1 , then the ss pin control must be enabled. 3: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the state of ss pin can affect the state read back from the trisb<5> bit. the peripheral oe signal from the ssp module into portb controls the state that is read back from the trisb<5> bit. if read- modify-write instructions, such as bsf , are performed on the trisb register while the ss pin is high, this will cause the trisb<5> bit to be set, thus disabling the sdo output. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 86h trisb portb data direction register 1111 1111 1111 1111 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the ssp in spi mode.
? 2003 microchip technology inc. preliminary ds30487b-page 91 pic16f87/88 figure 10-2: spi mode timing, master mode figure 10-3: spi mode timing (slave mode with cke = 0 ) figure 10-4: spi mode timing (slave mode with cke = 1 ) sck (ckp = 0 , sdi (smp = 0 ) sspif bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdi (smp = 1 ) sck (ckp = 0 , sck (ckp = 1 , sck (ckp = 1 , sdo bit 7 bit 7 bit 0 bit 0 cke = 0 ) cke = 1 ) cke = 0 ) cke = 1 ) sck (ckp = 0 ) sdi (smp = 0 ) sspif bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sck (ckp = 1 ) sdo bit 7 bit 0 ss (optional) sck (ckp = 0 ) sdi (smp = 0 ) sspif bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sck (ckp = 1 ) sdo bit 7 bit 0 ss
pic16f87/88 ds30487b-page 92 preliminary ? 2003 microchip technology inc. 10.3 ssp i 2 c mode operation the ssp module in i 2 c mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master func- tions. the ssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rb4/sck/scl pin, which is the clock (scl), and the rb1/sdi/sda pin, which is the data (sda). the user must configure these pins as inputs or outputs through the trisb<4,1> bits. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). figure 10-5: ssp block diagram (i 2 c mode) the ssp module has five registers for i 2 c operation: ssp control register (sspcon) ssp status register (sspstat) serial receive/transmit buffer register (sspbuf) ssp shift register (sspsr) - not directly accessible ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled to support firmware master mode i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled to support firmware master mode i 2 c firmware controlled master operation with start and stop bit interrupts enabled, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisb bits. pull-up resistors must be provided externally to the scl and sda pins for proper operation of the i 2 c module. additional information on ssp i 2 c operation may be found in the picmicro ? mid-range mcu reference manual (ds33023). 10.3.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisb<4,1> set). the ssp module will override the input state with the output data, when required (slave-transmitter). when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. either or both of the following conditions will cause the ssp module not to give this ack pulse: a) the buffer full bit, bf (sspstat<0>), was set before the transfer was received. b) the overflow bit, sspov (sspcon<6>), was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. table 10-2 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the overflow condi- tion. flag bit, bf, is cleared by reading the sspbuf register while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the ssp module, are shown in timing parameter #100 and parameter #101. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rb4/sck/ rb1/ shift clock msb sdi/ lsb sda scl
? 2003 microchip technology inc. preliminary ds30487b-page 93 pic16f87/88 10.3.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condi- tion, the eight bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf, is set. c) an ack pulse is generated. d) ssp interrupt flag bit, sspif (pir1<3>), is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave device. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 1111 0 a9 a8 0 ?, where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7- 9 for slave transmitter: 1. receive first (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address, if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. 10.3.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then a no acknowledge (ack ) pulse is given. an overflow condition is indicated if either bit, bf (sspstat<0>), is set or bit, sspov (sspcon<6>), is set. an ssp interrupt is generated for each data transfer byte. flag bit, sspif (pir1<3>), must be cleared in software. the sspstat register is used to determine the status of the byte. 10.3.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit, and pin rb4/sck/scl is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr regis- ter. then, pin rb4/sck/scl should be enabled by set- ting bit ckp (sspcon<4>). the master device must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master device by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 10-7). an ssp interrupt is generated for each data transfer byte. flag bit, sspif, must be cleared in software, and the sspstat register is used to determine the status of the byte. flag bit, sspif, is set on the falling edge of the ninth clock pulse. as a slave transmitter, the ack pulse from the master receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not ack ), then the data transfer is complete. when the ack is latched by the slave device, the slave logic is reset (resets sspstat register) and the slave device then monitors for another occurrence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr reg- ister. then, pin rb4/sck/scl should be enabled by setting bit ckp.
pic16f87/88 ds30487b-page 94 preliminary ? 2003 microchip technology inc. table 10-2: data transfer received byte actions figure 10-6: i 2 c waveforms for reception (7-bit address) figure 10-7: i 2 c waveforms for transmission (7-bit address) status bits as data transfer is received sspsr sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 yes yes yes 10 no no yes 11 no no yes 0 1 no no yes note 1: shaded cells show the conditions where the user software did not properly clear the overflow condition. p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 0 receiving address sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent sda scl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data is sampled scl held low while cpu responds to sspif (the sspbuf must be written to before the ckp bit can be set)
? 2003 microchip technology inc. preliminary ds30487b-page 95 pic16f87/88 10.3.2 master mode operation master mode operation is supported in firmware using interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset, or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle and both the s and p bits are clear. in master mode operation, the scl and sda lines are manipulated in firmware by clearing the corresponding trisb<4,1> bit(s). the output level is always low, irre- spective of the value(s) in portb<4,1>. so, when transmitting data, a ? 1 ? data bit must have the trisb<1> bit set (input) and a ? 0 ? data bit must have the trisb<1> bit cleared (output). the same scenario is true for the scl line with the trisb<4> bit. pull-up resistors must be provided externally to the scl and sda pins for proper operation of the i 2 c module. the following events will cause the ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received master mode operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ) or with the slave mode active. when both master mode operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt. for more information on master mode operation, see application note an554, ?software implementation of i 2 c? bus master? . 10.3.3 multi-master mode operation in multi-master mode operation, the interrupt genera- tion on the detection of the start and stop condi- tions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset, or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle and both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master mode operation, the sda line must be monitored to see if the signal level is the expected out- put level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set trisb<4,1>). there are two stages where this arbitration can be lost: address transfer data transfer when the slave logic is enabled, the slave device con- tinues to receive. if arbitration was lost during the address transfer stage, communication to the device may be in progress. if addressed, an ack pulse will be generated. if arbitration was lost during the data trans- fer stage, the device will need to re-transfer the data at a later time. for more information on multi-master mode operation, see application note an578, ?use of the ssp module in the of i 2 c? multi-master environment? . table 10-3: registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp (1) cke (1) d/a psr/w ua bf 0000 0000 0000 0000 86h trisb portb data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by ssp module in spi mode. note 1: maintain these bits clear in i 2 c mode.
pic16f87/88 ds30487b-page 96 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 97 pic16f87/88 11.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci.) the usart can be con- figured as a full-duplex asynchronous system that can communicate with peripheral devices, such as crt ter- minals and personal computers, or it can be configured as a half-duplex synchronous system that can commu- nicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the usart can be configured in the following modes: asynchronous (full-duplex) synchronous - master (half-duplex) synchronous - slave (half-duplex) bit spen (rcsta<7>) and bits trisb<5,2> have to be set in order to configure pins, rb5/ss /tx/ck and rb2/sdo/rx/dt, as the universal synchronous asynchronous receiver transmitter. the usart module also has a multi-processor communication capability, using 9-bit address detection. register 11-1: txsta: transmit status and control register (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ? brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as ? 0 ? bit 2 brgh : high baud rate select bit asynchronous mode: 1 = high-speed 0 = low-speed synchronous mode: unused in this mode. bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data, can be parity bit legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 98 preliminary ? 2003 microchip technology inc. register 11-2: rcsta: receive status and control register (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rb2/sdo/rx/dt and rb5/ss /tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode: don?t care. synchronous mode - master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - slave: don?t care. bit 4 cren : continuous receive enable bit asynchronous mode: 1 = enables continuous receive 0 = disables continuous receive synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ): 1 = enables address detection, enables interrupt and load of the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data (can be parity bit, but must be calculated by user firmware) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 99 pic16f87/88 11.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free-running 8-bit timer. in asynchronous mode, bit brgh (txsta<2>) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 11-1 shows the formula for computation of the baud rate for different usart modes, which only apply in master mode (internal clock). given the desired baud rate and f osc , the nearest integer value for the spbrg register can be calculated using the formula in table 11-1. from this, the error in baud rate can be determined. it may be advantageous to use the high baud rate (brgh = 1 ) even for slower baud clocks. this is because the f osc /(16(x + 1 )) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 11.1.1 usart and intrc operation the pic16f87/88 has an 8 mhz intrc that can be used as the system clock, thereby eliminating the need for external components to provide the clock source. when the intrc provides the system clock, the usart module will also use the intrc as its system clock. table 11-1 shows some of the intrc fre- quencies that can be used to generate the usart?s baud rate. 11.1.2 low-power mode operation the system clock is used to generate the desired baud rate; however, when a low-power mode is entered, the low-power clock source may be operating at a different frequency than in full power execution. in sleep mode, no clocks are present. this may require the value in spbrg to be adjusted. 11.1.3 sampling the data on the rb2/sdo/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. table 11-1: baud rate formula table 11-2: registers associated with baud rate generator sync brgh = 0 (low-speed) brgh = 1 (high-speed) 0 1 (asynchronous) baud rate = f osc /(64(x + 1)) (synchronous) baud rate = f osc /(4(x + 1)) baud rate = f osc /(16(x + 1)) n/a legend: x = value in spbrg (0 to 255) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used by the brg.
pic16f87/88 ds30487b-page 100 preliminary ? 2003 microchip technology inc. table 11-3: baud rates for asynchronous mode (brgh = 0 ) baud rate (k) f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3????????? 1.2 1.221 +1.75 255 1.202 +0.17 207 1.202 +0.17 129 2.4 2.404 +0.17 129 2.404 +0.17 103 2.404 +0.17 64 9.6 9.766 +1.73 31 9.615 +0.16 25 9.766 +1.73 15 19.2 19.531 + 1.72 15 19.231 +0.16 12 19.531 +1.72 7 28.8 31.250 +8.51 9 27.778 -3.55 8 31.250 +8.51 4 33.6 34.722 +3.34 8 35.714 +6.29 6 31.250 -6.99 4 57.6 62.500 +8.51 4 62.500 +8.51 3 52.083 -9.58 2 high 1.221 ? 255 0.977 ? 255 0.610 ? 255 low 312.500 ? 0 250.000 ? 0 156.250 ? 0 baud rate (k) f osc = 4 mhz f osc = 3.6864 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 0.300 0 207 0.3 0 191 1.2 1.202 +0.17 51 1.2 0 47 2.4 2.404 +0.17 25 2.4 0 23 9.6 8.929 +6.99 6 9.6 0 5 19.2 20.833 +8.51 2 19.2 0 2 28.8 31.250 +8.51 1 28.8 0 1 33.6 ? ? ? ? ? ? 57.6 62.500 +8.51 0 57.6 0 0 high 0.244 ? 255 0.225 ? 255 low 62.500 ? 0 57.6 ? 0 table 11-4: baud rates for asynchronous mode (brgh = 1 ) baud rate (k) f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3????????? 1.2????????? 2.4 ? ? ? ? ? ? 2.441 +1.71 255 9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 19.2 19.231 +0.16 64 19.231 +0.16 51 19.531 +1.72 31 28.8 29.070 +0.94 42 29.412 +2.13 33 28.409 -1.36 21 33.6 33.784 +0.55 36 33.333 -0.79 29 32.895 -2.10 18 57.6 59.524 +3.34 20 58.824 +2.13 16 56.818 -1.36 10 high 4.883 ? 255 3.906 ? 255 2.441 ? 255 low 1250.000 ? 0 1000.000 ? 0 625.000 ? 0 baud rate (k) f osc = 4 mhz f osc = 3.6864 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3?????? 1.2 1.202 +0.17 207 1.2 0 191 2.4 2.404 +0.17 103 2.4 0 95 9.6 9.615 +0.16 25 9.6 0 23 19.2 19.231 +0.16 12 19.2 0 11 28.8 27.798 -3.55 8 28.8 0 7 33.6 35.714 +6.29 6 32.9 -2.04 6 57.6 62.500 +8.51 3 57.6 0 3 high 0.977 ? 255 0.9 ? 255 low 250.000 ? 0 230.4 ? 0
? 2003 microchip technology inc. preliminary ds30487b-page 101 pic16f87/88 table 11-5: intrc baud rates fo r asynchronous mode (brgh = 0 ) baud rate (k) f osc = 8 mhz f osc = 4 mhz f osc = 2 mhz f osc = 1 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 na ? ? 0.300 0 207 0.300 0 103 0.300 0 51 1.2 1.202 +0.16 103 1.202 +0.16 51 1.202 +0.16 25 1.202 +0.16 12 2.4 2.404 +0.16 51 2.404 +0.16 25 2.404 +0.16 12 2.232 -6.99 6 9.6 9.615 +0.16 12 8.929 -6.99 6 10.417 +8.51 2 na ? ? 19.2 17.857 -6.99 6 20.833 +8.51 2 na ? ? na ? ? 28.8 31.250 +8.51 3 31.250 +8.51 1 31.250 +8.51 0 na ? ? 38.4 41.667 +8.51 2 na ? ? na ? ? na ? ? 57.6 62.500 +8.51 1 62.500 8.51 0 na ? ? na ? ? table 11-6: intrc baud rates fo r asynchronous mode (brgh = 1 ) baud rate (k) f osc = 8 mhz f osc = 4 mhz f osc = 2 mhz f osc = 1 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 na ? ? na ? ? na ? ? 0.300 0 207 1.2 na ? ? 1.202 +0.16 207 1.202 +0.16 103 1.202 +0.16 51 2.4 2.404 +0.16 207 2.404 +0.16 103 2.404 +0.16 51 2.404 +0.16 25 9.6 9.615 +0.16 51 9.615 +0.16 25 9.615 +0.16 12 8.929 -6.99 6 19.2 19.231 +0.16 25 19.231 +0.16 12 17.857 -6.99 6 20.833 +8.51 2 28.8 29.412 +2.12 16 27.778 -3.55 8 31.250 +8.51 3 31.250 +8.51 1 38.4 38.462 +0.16 12 35.714 -6.99 6 41.667 +8.51 2 na ? ? 57.6 55.556 -3.55 8 62.500 +8.51 3 62.500 +8.51 1 62.500 +8.51 0
pic16f87/88 ds30487b-page 102 preliminary ? 2003 microchip technology inc. 11.2 usart asynchronous mode in this mode, the usart uses standard non-return-to- zero (nrz) format (one start bit, eight or nine data bits, and one stop bit). the most common data format is 8 bits. an on-chip, dedicated, 8-bit baud rate gener- ator can be used to derive standard baud rate frequen- cies from the oscillator. the usart transmits and receives the lsb first. the transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 11.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 11-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit, txif (pir1<4>), is set. this inter- rupt can be enabled/disabled by setting/clearing enable bit, txie (pie1<4>). flag bit txif will be set, regardless of the state of enable bit txie and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr reg- ister. status bit trmt is a read-only bit, which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 11-2). the transmission can also be started by first loading the txreg register and then setting enable bit txen. normally, when transmission is first started, the tsr register is empty. at that point, transfer to the txreg register will result in an immedi- ate transfer to tsr, resulting in an empty txreg. a back-to-back transfer is thus possible (figure 11-3). clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. as a result, the rb5/ss /tx/ck pin will revert to high-impedance. in order to select 9-bit transmission, transmit bit, tx9 (txsta<6>), should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg reg- ister. this is because a data write to the txreg regis- ter can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit may be loaded in the tsr register. figure 11-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif is cleared by loading txreg. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rb5/ss /tx/ck pin pin buffer and control 8 ? ? ?
? 2003 microchip technology inc. preliminary ds30487b-page 103 pic16f87/88 when setting up an asynchronous transmission, follow these steps: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 11.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts transmission). 8. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. figure 11-2: asynchronous master transmission figure 11-3: asynchronous master transmission (back to back) table 11-7: registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if -000 000x -000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rb5/ss /tx/ck pin txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) transmit shift reg. write to txreg brg output (shift clock) rb5/ss /tx/ck pin txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows tw o consecutive transmissions.
pic16f87/88 ds30487b-page 104 preliminary ? 2003 microchip technology inc. 11.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 11-4. the data is received on the rb2/sdo/rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter, operating at x16 times the baud rate; whereas, the main receive serial shifter operates at the bit rate or at f osc . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift register (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, flag bit, rcif (pir1<5>), is set. the actual interrupt can be enabled/disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit, which is cleared by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is a double buffered register (i.e., it is a two-deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting to the rsr register. on the detection of the stop bit of the third byte, if the rcreg register is still full, the overrun error bit, oerr (rcsta<1>), will be set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. overrun bit oerr has to be cleared in soft- ware. this is done by resetting the receive logic (cren is cleared and then set). if bit oerr is set, transfers from the rsr register to the rcreg register are inhib- ited, and no further data will be received. it is, therefore, essential to clear error bit oerr if it is set. framing error bit, ferr (rcsta<2>), is set if a stop bit is detected as clear. bit ferr and the 9th receive bit are buffered the same way as the receive data. reading the rcreg will load bits rx9d and ferr with new values, therefore, it is essential for the user to read the rcsta register before reading the rcreg register, in order not to lose the old ferr and rx9d information. figure 11-4: usart receive block diagram figure 11-5: asynchronous reception x64 baud rate clk spbrg baud rate generator rb2/sdo/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? f osc start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx pin reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set.
? 2003 microchip technology inc. preliminary ds30487b-page 105 pic16f87/88 when setting up an asynchronous reception, follow these steps: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 11.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit rcie. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie is set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 11-8: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception.
pic16f87/88 ds30487b-page 106 preliminary ? 2003 microchip technology inc. 11.2.3 setting up 9-bit mode with address detect when setting up an asynchronous reception with address detect enabled: initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh. enable the asynchronous serial port by clearing bit sync and setting bit spen. if interrupts are desired, then set enable bit rcie. set bit rx9 to enable 9-bit reception. set adden to enable address detect. enable the reception by setting enable bit cren. flag bit rcif will be set when reception is com- plete, and an interrupt will be generated if enable bit rcie was set. read the rcsta register to get the ninth bit and determine if any error occurred during reception. read the 8-bit received data by reading the rcreg register, to determine if the device is being addressed. if any error occurred, clear the error by clearing enable bit cren. if the device has been addressed, clear the adden bit to allow data bytes and address bytes to be read into the receive buffer, and interrupt the cpu. figure 11-6: usart receive block diagram x64 baud rate clk spbrg baud rate generator rb2/sdo/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? rx9 adden rx9 adden rsr<8> enable load of receive buffer 8 8 f osc
? 2003 microchip technology inc. preliminary ds30487b-page 107 pic16f87/88 figure 11-7: asynchronous reception with address detect figure 11-8: asynchronous reception with address byte first table 11-9: registers associated with asynchronous reception start bit bit 1 bit 0 bit 8 bit 0 stop bit start bit bit 8 rb2/sdo/rx/dt pin load rsr read rcif word 1 rcreg bit 8 = 0 , data byte bit 8 = 1 , address byte note: this timing diagram shows a data byte followed by an address byte. the data byte is not read into the rcreg (receive buffer) because adden = 1 . stop bit start bit bit 1 bit 0 bit 8 bit 0 stop bit start bit bit 8 rb2/sdo/rx/dt pin load rsr rcif word 1 rcreg bit 8 = 1 , address byte bit 8 = 0 , data byte note: this timing diagram shows a data byte followed by an address byte. the data byte is not read into the rcreg (receive buffer) because adden was not updated and still = 0 . read stop bit address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception.
pic16f87/88 ds30487b-page 108 preliminary ? 2003 microchip technology inc. 11.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition, enable bit spen (rcsta<7>) is set in order to configure the rb5/ss /tx/ck and rb2/sdo/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor trans- mits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 11.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 11-6. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cycle ), the txreg is empty and inter- rupt bit txif (pir1<4>) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set, regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr register. trmt is a read only bit which is set when the tsr is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory, so it is not available to the user. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the first data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is sta- ble around the falling edge of the synchronous clock (figure 11-9). the transmission can also be started by first loading the txreg register and then setting bit txen (figure 11-10). this is advantageous when slow baud rates are selected, since the brg is kept in reset when bits txen, cren and sren are clear. setting enable bit txen will start the brg, creating a shift clock immediately. normally, when transmission is first started, the tsr register is empty, so a transfer to the txreg register will result in an immediate transfer to tsr, resulting in an empty txreg. back-to-back transfers are possible. clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to high- impedance. if either bit cren or bit sren is set during a transmission, the transmission is aborted and the dt pin reverts to a hi-impedance state (for a reception). the ck pin will remain an output if bit csrc is set (internal clock). the transmitter logic, however, is not reset, although it is disconnected from the pins. in order to reset the transmitter, the user has to clear bit txen. if bit sren is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit sren will be cleared and the serial port will revert back to transmitting, since bit txen is still set. the dt line will immediately switch from high- impedance receive mode to transmit and start driving. to avoid this, bit txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr was empty and the txreg was written before writing the ?new? tx9d, the ?present? value of bit tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate ( section 11.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set.
? 2003 microchip technology inc. preliminary ds30487b-page 109 pic16f87/88 table 11-10: registers associated with synchronous master transmission figure 11-9: synchronous transmission figure 11-10: synchronous transmission (through txen) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rb2/sdo/ rb5/ss /tx/ write to txreg reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode; spbrg = 0 . continuous transmission of two 8-bit words. rx/dt pin ck pin rb2/sdo/rx/dt pin rb5/ss /tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit
pic16f87/88 ds30487b-page 110 preliminary ? 2003 microchip technology inc. 11.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>), or enable bit cren (rcsta<4>). data is sampled on the rb2/sdo/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, cren takes precedence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, interrupt flag bit, rcif (pir1<5>), is set. the actual interrupt can be enabled/disabled by setting/ clearing enable bit rcie (pie1<5>). flag bit rcif is a read-only bit, which is reset by the hardware. in this case, it is reset when the rcreg register has been read and is empty. the rcreg is a double-buffered register (i.e., it is a two-deep fifo). it is possible for two bytes of data to be received and trans- ferred to the rcreg fifo and a third byte to begin shift- ing into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full, then overrun error bit, oerr (rcsta<1>), is set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. bit oerr has to be cleared in software (by clearing bit cren). if bit oerr is set, transfers from the rsr to the rcreg are inhibited, so it is essential to clear bit oerr if it is set. the ninth receive bit is buffered the same way as the receive data. reading the rcreg register will load bit rx9d with a new value, therefore, it is essential for the user to read the rcsta register before reading rcreg, in order not to lose the old rx9d information. when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate ( section 11.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit, rcif, will be set when reception is complete and an interrupt will be generated if enable bit, rcie, was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 11-11: registers associated with synchronous master reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception.
? 2003 microchip technology inc. preliminary ds30487b-page 111 pic16f87/88 figure 11-11: synchronous reception (master mode, sren) 11.4 usart synchronous slave mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rb5/ss /tx/ck pin (instead of being supplied inter- nally in master mode). this allows the device to trans- fer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 11.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in the txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). when setting up a synchronous slave transmission, follow these steps: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 11-12: registers associated with synchronous slave transmission cren bit rb2/sdo/rx/dt rb5/ss /tx/ck write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brg = 0 . q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 pin pin address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission.
pic16f87/88 ds30487b-page 112 preliminary ? 2003 microchip technology inc. 11.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. bit sren is a ?don't care? in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). when setting up a synchronous slave reception, follow these steps: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete and an interrupt will be generated, if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 11-13: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 ? adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 ? adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception.
? 2003 microchip technology inc. preliminary ds30487b-page 113 pic16f87/88 12.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has seven inputs for 18/20 pin devices (pic16f88 devices only). the conversion of an analog input signal results in a corresponding 10-bit digital number. the a/d module has a high and low voltage reference input that is soft- ware selectable to some combination of v dd , v ss , v ref - (ra2), or v ref + (ra3). the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the a/d module has five registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) analog select register (ansel) the adcon0 register, shown in register 12-2, con- trols the operation of the a/d module. the ansel reg- ister, shown in register 12-1 and the adcon1 register, shown in register 12-3, configure the functions of the port pins. the port pins can be configured as analog inputs (ra3/ra2 can also be voltage references) or as digital i/o. additional information on using the a/d module can be found in the picmicro ? mid-range mcu family reference manual (ds33023). register 12-1: ansel register (address 9bh) pic16f88 devices only u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ans6 ans5 ans4 ans3 ans2 ans1 ans0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-0 ans<6:0>: analog input select bits bits select input function on corresponding an<6:0> pins. 1 = analog i/o (see notes below) 0 = digital i/o note 1: setting a pin to an analog input disables the digital input buffer. the corresponding tris bit should be set to input mode when using pins as analog inputs. only an2 is an analog i/o, all other anx pins are analog inputs. 2: see the block diagrams for the analog i/o pins to see how ansel interacts with the chs bits of the adcon0 register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 114 preliminary ? 2003 microchip technology inc. register 12-2: adcon0 register (address 1fh) pic16f88 devices only r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon bit 7 bit 0 bit 7-6 adcs<1:0>: a/d conversion clock select bits if adsc2 = 0 : 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from the internal a/d module rc oscillator) if adsc2 = 1 : 00 = f osc /4 01 = f osc /16 10 = f osc /64 11 = f rc (clock derived from the internal a/d module rc oscillator) bit 5-3 chs<2:0>: analog channel select bits 000 = channel 0 (ra0/an0) 001 = channel 1 (ra1/an1) 010 = channel 2 (ra2/an2) 011 = channel 3 (ra3/an3) 100 = channel 4 (ra4/an4) 101 = channel 5 (rb6/an5) 110 = channel 6 (rb7/an6) bit 2 go/done : a/d conversion status bit if adon = 1 : 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1 unimplemented: read as ? 0 ? bit 0 adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shut-off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 115 pic16f87/88 register 12-3: adcon1 register (address 9fh) pic16f88 devices only r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 adfm adcs2 vcfg1 vcfg0 ? ? ? ? bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified. six most significant bits of adresh are read as ? 0 ?. 0 = left justified. six least significant bits of adresl are read as ? 0 ?. bit 6 adcs2: a/d clock divide by 2 select bit 1 = a/d clock source is divided by 2 when system clock is used 0 =disabled bit 5-4 vcfg<1:0>: a/d voltage reference configuration bits note: the ansel bits for an3 and an2 inputs must be configured as analog inputs for the v ref + and v ref - external pins to be used. bit 3-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown logic state v ref +v ref - 00 av dd av ss 01 av dd v ref- 10 v ref+ av ss 11 v ref+ v ref-
pic16f87/88 ds30487b-page 116 preliminary ? 2003 microchip technology inc. the adresh:adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the a/d result register pair, the go/done bit (adcon0<2>) is cleared, and a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 12-1. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine sample time, see section 12.1. after this sample time has elapsed, the a/d conversion can be started. these steps should be followed for doing an a/d conversion: 1. configure the a/d module: configure analog/digital i/o (ansel) configure voltage reference (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set peie bit set gie bit 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared (with interrupts disabled); or waiting for the a/d interrupt 6. read a/d result register pair (adresh:adresl), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. figure 12-1: a/d block diagram (input voltage) v in v ref + (reference voltage) av dd vcfg1:vcfg0 chs2:chs0 ra3/an3/v ref +/c1out ra2/an2/cv ref /v ref - ra1/an1 ra0/an0 011 010 001 000 a/d converter v ref - (reference voltage) av ss vcfg1:vcfg0 rb6/an5/pgc/t1oso/t1cki rb7/an6/pgd/t1osi ra4/an4/t0cki/c2out 110 101 100
? 2003 microchip technology inc. preliminary ds30487b-page 117 pic16f87/88 12.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 12-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 12-2. the maximum recom- mended impedance for analog sources is 2.5 k ? . as the impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 12-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. to calculate the minimum acquisition time, t acq , see the picmicro ? mid-range reference manual (ds33023). equation 12-1: acquisition time figure 12-2: analog input model t acq t c t acq = = = = = = = = amplifier settling time + hold capacitor charging time + temperature coefficient t amp + t c + t coff 2 s + t c + [(temperature -25 c)(0.05 s/c)] c hold (r ic + r ss + r s ) in(1/2047) -120 pf (1 k ? + 7 k ? + 10 k ? ) in(0.0004885) 16.47 s 2 s + 16.47 s + [(50c ? 25 c)(0.05 s/ c) 19.72 s note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification. 4: after a conversion has completed, a 2.0 t ad delay must complete before acquisition can begin again. during this time, the holding capacitor is not connected to the selected a/d input channel. c pin va rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6 v sampling switch 5 v 4 v 3 v 2 v 567891011 (k ? ) v dd = 51.2 pf 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
pic16f87/88 ds30487b-page 118 preliminary ? 2003 microchip technology inc. 12.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 9.0 t ad per 8-bit conversion. the source of the a/d conversion clock is software selectable. the seven possible options for t ad are: 2t osc 4t osc 8t osc 16t osc 32t osc 64t osc internal a/d module rc oscillator (2-6 s) for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time as small as possible, but no less than 1.6 s and not greater than 6.4 s. table 12-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 12.3 configuring analog port pins the adcon1, ansel, trisa, and trisb registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their cor- responding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs<2:0> bits and the tris bits. table 12-1: t ad vs. maximum device operating frequencies ? standard devices (c) note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an ana- log input. analog levels on a digitally configured input will not affect the conversion accuracy. 2: analog levels on any pin that is defined as a digital input (including the ra4:ra0 and rb7:rb6 pins), may cause the input buffer to consume current out of the device specification. ad clock source (t ad ) maximum device frequency operation adcs<2> adcs<1:0> max. 2 t osc 000 1.25 mhz 4 t osc 100 2.5 mhz 8 t osc 001 5 mhz 16 t osc 101 10 mhz 32 t osc 010 20 mhz 64 t osc 110 20 mhz rc (1,2,3) x11 (note 1) note 1: the rc source has a typical t ad time of 4 s, but can vary between 2-6 s. 2: when the device frequencies are greater than 1 mhz, the rc a/d conversion clock source is only recommended for sleep operation. 3: for extended voltage devices (lf), please refer to section 18.0 ?electrical characteristics? .
? 2003 microchip technology inc. preliminary ds30487b-page 119 pic16f87/88 12.4 a/d conversions clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is aborted, a 2 t ad wait is required before the next acquisition is started. after this 2 t ad wait, acquisition on the selected channel is automatically started. the go/done bit can then be set to start the conversion. in figure 12-3, after the go bit is set, the first time segment has a minimum of t cy and a maximum of t ad . 12.4.1 a/d result registers the adresh:adresl register pair is the location where the 10-bit a/d result is loaded at the completion of the a/d conversion. this register pair is 16 bits wide. the a/d module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. the a/d format select bit (adfm) controls this justification. figure 12-4 shows the operation of the a/d result justification. the extra bits are loaded with ? 0 ?s. when an a/d result will not overwrite these locations (a/d dis- able), these registers may be used as two general purpose 8-bit registers. figure 12-3: a/d conversion t ad cycles figure 12-4: a/d result justification note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 set go bit holding capacitor is disconnected fr om analog input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 t ad 10 t ad 11 b1 b0 t cy to t ad conversion starts adres is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input 10-bit result adresh adresl 0000 00 adfm = 0 0 2 1 0 7 7 10-bit result adresh adresl 10-bit result 0000 00 7 0 7 6 5 0 adfm = 1 right justified left justified
pic16f87/88 ds30487b-page 120 preliminary ? 2003 microchip technology inc. 12.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed, the go/done bit will be cleared and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d mod- ule will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 12.6 effects of a reset a device reset forces all registers to their reset state. the a/d module is disabled and any conversion in progress is aborted. all a/d input pins are configured as analog inputs. the value that is in the adresh:adresl registers is not modified for a power-on reset. the adresh:adresl registers will contain unknown data after a power-on reset. 12.7 use of the ccp trigger an a/d conversion can be started by the ?special event trigger? of the ccp module. this requires that the ccp1m3:ccp1m0 bits (ccp1con<3:0>) be pro- grammed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/ done bit will be set, starting the a/d conversion and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adresh:adresl to the desired location). the appro- priate analog input channel must be selected and the minimum acquisition done before the ?special event trigger? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ?special event trigger? will be ignored by the a/d module, but will still reset the timer1 counter. note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an a/d conversion in sleep, ensure the sleep instruction immediately follows the instruction that sets the go/done bit. table 12-2: registers/bits associated with a/d address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 ?adif rcif txif sspif ccp1if tmr2if tmr1if -000 0000 -000 0000 8ch pie1 ?adie rcie txie sspie ccp1ie tmr2ie tmr1ie -000 0000 -000 0000 1eh adresh (1) a/d result register high byte xxxx xxxx uuuu uuuu 9eh adresl (1) a/d result register low byte xxxx xxxx uuuu uuuu 1fh adcon0 (1) adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 0000 00-0 9fh adcon1 (1) adfm adcs2 vcfg1 vcfg0 ? ? ? ? 0000 ---- 0000 ---- 9bh ansel (1) ? an6 an5 an4 an3 an2 an1 an0 -111 1111 -111 1111 05h porta (pic16f87) (pic16f88) ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0000 xxx0 0000 uuuu 0000 uuu0 0000 05h, 106h portb (pic16f87) (pic16f88) rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx 00xx xxxx uuuu uuuu 00uu uuuu 85h trisa trisa7 trisa6 trisa5 (2) porta data direction register 1111 1111 1111 1111 86h, 186h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: pic16f88 only. 2: pin 5 is an input only; the st ate of the trisa5 bit has no effect and will always read ? 1 ?.
? 2003 microchip technology inc. preliminary ds30487b-page 121 pic16f87/88 13.0 comparator module the comparator module contains two analog comparators. the inputs to the comparators are multi- plexed with i/o port pins ra0 through ra3, while the outputs are multiplexed to pins ra3 and ra4. the on- chip voltage reference ( section 14.0 ?comparator voltage reference module? ) can also be an input to the comparators. the cmcon register (register 13-1) controls the com- parator input and output multiplexers. a block diagram of the various comparator configurations is shown in figure 13-1. register 13-1: cmcon register (address 9ch) r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out: comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out: comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv: comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv: comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis: comparator input switch bit when cm2:cm0 = 001 : 1 =c1 v in - connects to ra3 0 =c1 v in - connects to ra0 when cm2:cm0 = 010 : 1 =c1 v in - connects to ra3 c2 v in - connects to ra2 0 =c1 v in - connects to ra0 c2 v in - connects to ra1 bit 2-0 cm<2:0>: comparator mode bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 122 preliminary ? 2003 microchip technology inc. 13.1 comparator configuration there are eight modes of operation for the compara- tors. the cmcon register is used to select these modes. figure 13-1 shows the eight possible modes. the trisa register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in section 18.0 ?electrical characteristics? . figure 13-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change. otherwise, a false interrupt may occur. c1 ra0/an0 v in - v in + ra3/an3 off (read as ? 0 ?) comparators reset a a cm2:cm0 = 000 c2 ra1/an1 v in - v in + ra2/an2 off (read as ? 0 ?) a a c1 ra0/an0 v in - v in + ra3/an3 c1out two independent comparators a a cm2:cm0 = 100 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators a d cm2:cm0 = 011 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 off (read as ? 0 ?) one independent comparator d d cm2:cm0 = 101 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 off (read as ? 0 ?) comparators off (por default value) d d cm2:cm0 = 111 c2 ra1/an1 v in - v in + ra2/an2 off (read as ? 0 ?) d d c1 ra0/an0 v in - v in + ra3/an3 c1out four inputs multiplexed to two comparators a a cm2:cm0 = 010 c2 ra1/an1 v in - v in + ra2/an2 c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators with outputs a d cm2:cm0 = 110 c2 ra1/an1 v in - v in + ra2/an2 c2out a a a = analog input, port reads zeros always. d = digital input. cis (cmcon<3>) is the comparator input switch. ra4/t0cki c1 ra0/an0 v in - v in + ra3/an3 c1out three inputs multiplexed to two comparators a a cm2:cm0 = 001 c2 ra1/an1 v in - v in + ra2/an2 c2out a a cis = 0 cis = 1
? 2003 microchip technology inc. preliminary ds30487b-page 123 pic16f87/88 13.2 comparator operation a single comparator is shown in figure 13-2, along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 13-2 represent the uncertainty due to input offsets and response time. 13.3 comparator reference an external or internal reference signal may be used depending on the comparator operating mode. the analog signal present at v in - is compared to the signal at v in +, and the digital output of the comparator is adjusted accordingly (figure 13-2). figure 13-2: single comparator 13.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same, or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd , and can be applied to either pin of the comparator(s). 13.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the comparators. section 14.0 ?comparator voltage reference module? contains a detailed description of the comparator voltage reference module that pro- vides this signal. the internal reference signal is used when comparators are in mode cm<2:0> = 110 (figure 13-1). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 13.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal reference is changed, the maximum delay of the inter- nal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used ( section 18.0 ?electrical characteristics? ). 13.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read only. the comparator outputs may also be directly output to the ra3 and ra4 i/o pins. when enabled, multiplexors in the output path of the ra3 and ra4 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 13-3 shows the comparator output block diagram. the trisa bits will still function as an output enable/ disable for the ra3 and ra4 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<4:5>). ? + v in + v in - output v in? v in+ o utput output v in + v in - note 1: when reading the port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert an analog input, according to the schmitt trigger input specification. 2: analog levels, on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.
pic16f87/88 ds30487b-page 124 preliminary ? 2003 microchip technology inc. figure 13-3: comparator output block diagram 13.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir registers) is the comparator interrupt flag. the cmif bit must be reset by clearing it (? 0 ?). since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. the cmie bit (pie registers) and the peie bit (intcon register) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition, and allow flag bit cmif to be cleared. d q en rd_cmcon set cmif bit multiplex d q en cl port pins q3 * rd_cmcon nreset from other comparator to data bus q1 cninv note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir registers) interrupt flag may not get set.
? 2003 microchip technology inc. preliminary ds30487b-page 125 pic16f87/88 13.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional, if enabled. this interrupt will wake-up the device from sleep mode when enabled. while the comparator is powered up, higher sleep currents than shown in the power-down current specification will occur. each operational comparator will consume additional current, as shown in the com- parator specifications. to minimize power consumption while in sleep mode, turn off the comparators, cm<2:0> = 111 , before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 13.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator module to be in the comparator off mode, cm<2:0> = 111 . 13.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 13-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k ? is rec- ommended for the analog sources. any external com- ponent connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 13-4: analog input model va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage
pic16f87/88 ds30487b-page 126 preliminary ? 2003 microchip technology inc. table 13-1: registers associated with the comparator module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 0bh, 8bh, 10bh, 18bh intcon gie peie tmr0ie intie rbie tmr0if intif rbif 0000 000x 0000 000u 0dh pir2 osfif cmif ? eeif ? ? ? ? 00-0 ---- 00-0 ---- 8dh pie2 osfie cmie ? eeie ? ? ? ? 00-0 ---- 00-0 ---- 05h porta (pic16f87) (pic16f88) ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0000 xxx0 0000 uuuu 0000 uuu0 0000 85h trisa trisa7 trisa6 trisa5 (1) trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are unused by the comparator module. note 1: pin 5 is an input only; the state of the tr isa5 bit has no effect and will always read ? 1 ?.
? 2003 microchip technology inc. preliminary ds30487b-page 127 pic16f87/88 14.0 comparator voltage reference module the comparator voltage reference generator is a 16- tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode ? 110 ?. a programmable register controls the function of the ref- erence generator. register 14-1 lists the bit functions of the cvrcon register. as shown in figure 14-1, the resistor ladder is seg- mented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the comparator reference supply voltage (also referred to as cv rsrc ) comes directly from v dd . it should be noted, however, that the voltage at the top of the ladder is cv rsrc ? v sat , where v sat is the saturation voltage of the power switch transistor. this reference will only be as accurate as the values of cv rsrc and v sat . the output of the reference generator may be con- nected to the ra2/an2/cv ref /v ref - pin. this can be used as a simple d/a function by the user, if a very high-impedance load is used. the primary purpose of this function is to provide a test path for testing the reference generator function. register 14-1: cvrcon control register (address 9dh) r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 bit 7 cvren: comparator voltage reference enable bit 1 = cv ref circuit powered on 0 = cv ref circuit powered down bit 6 cvroe: comparator v ref output enable bit 1 = cv ref voltage level is output on the ra2/an2/cv ref /v ref - pin 0 = cv ref voltage level is disconnected from the ra2/an2/cv ref /v ref - pin bit 5 cvrr: comparator v ref range selection bit 1 = 0.00 cv rsrc to 0.75 cv rsrc with cv rsrc /24 step size 0 = 0.25 cv rsrc to 0.75 cv rsrc with cv rsrc /32 step size bit 4 unimplemented: read as ? 0 ? bit 3-0 cvr<3:0>: comparator v ref value selection 0 vr3:vr0 15 bits when cvrr = 1 : cv ref = (vr<3:0>/24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (vr3:vr0/32) ? (cv rsrc ) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 128 preliminary ? 2003 microchip technology inc. figure 14-1: comparator voltage reference block diagram table 14-1: registers associated with comparator voltage reference cvrr 8r cvr3 cvr0 16-1 analog mux 8r r r r r cvren cv ref 16 stages input to comparator cvroe ra2/an2/cv ref /v ref - pin v dd cvr2 cvr1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used with the comparator voltage reference.
? 2003 microchip technology inc. preliminary ds30487b-page 129 pic16f87/88 15.0 special features of the cpu these devices have a host of features intended to max- imize system reliability, minimize cost through elimina- tion of external components, provide power saving operating modes and offer code protection: reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) two-speed start-up fail-safe clock monitor sleep code protection id locations in-circuit serial programming? (icsp?) there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. it is designed to keep the part in reset while the power supply stabilizes, and is enabled or disabled using a configuration bit. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. additional information on special features is available in the picmicro ? mid-range reference manual (ds33023). 15.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select vari- ous device configurations. these bits are mapped in program memory locations 2007h and 2008h. the user will note that address 2007h is beyond the user program memory space, which can be accessed only during programming.
pic16f87/88 ds30487b-page 130 preliminary ? 2003 microchip technology inc. register 15-1: config1: configuration word 1 register (addr ess 2007h) r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cp ccpmx resv wrt1 wrt0 cpd lvp boren mclre f osc 2pwrten wdten f osc 1f osc 0 bit 13 bit 0 bit 13 cp: flash program memory code protection bits 1 = code protection off 0 = 0000h to 0fffh code protected (all protected) bit 12 ccpmx: ccp1 pin selection bit 1 = ccp1 function on rb0 0 = ccp1 function on rb3 bit 11 debug: in-circuit debugger mode bit 1 = in-circuit debugger disabled, rb6 and rb7 are general purpose i/o pins 0 = in-circuit debugger enabled, rb6 and rb7 are dedicated to the debugger bit 10-9 wrt<1:0>: flash program memory write enable bits 11 = write protection off 10 = 0000h to 00ffh write protected, 0100h to 0fffh may be modified by eecon control 01 = 0000h to 07ffh write protected, 0800h to 0fffh may be modified by eecon control 00 = 0000h to 0fffh write protected bit 8 cpd: data ee memory code protection bit 1 = code protection off 0 = data ee memory code protected bit 7 lvp: low-voltage programming enable bit 1 = rb3/pgm pin has pgm function, low-voltage programming enabled 0 = rb3 is digital i/o, hv on mclr must be used for programming bit 6 boren: brown-out reset enable bit 1 = bor enabled 0 = bor disabled bit 5 mclre: ra5/mclr pin function select bit 1 = ra5/mclr pin function is mclr 0 = ra5/mclr pin function is digital i/o, mclr internally tied to v dd bit 3 pwrten : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 2 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 4, 1-0 f osc <2:0>: oscillator selection bits 111 = extrc oscillator; clko function on ra6/osc2/clko 110 = extrc oscillator; port i/o function on ra6/osc2/clko 101 = intrc oscillator; clko function on ra6/osc2/clko pin and port i/o function on ra7/osc1/clki pin 100 = intrc oscillator; port i/o function on both ra6/osc2/clko pin and ra7/osc1/clki pin 011 = extclk; port i/o function on ra6/osc2/clko 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30487b-page 131 pic16f87/88 register 15-2: config2: configuration word 2 register (addr ess 2008h) u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 r/p-1 r/p-1 ? ? ? ? ? ? ? ? ? ? ? ? ieso fcmen bit 13 bit 0 bit 13-2 unimplemented: read as ? 1 ? bit 1 ieso: internal external switch over bit 1 = internal external switch over mode enabled 0 = internal external switch over mode disabled bit 0 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87/88 ds30487b-page 132 preliminary ? 2003 microchip technology inc. 15.2 reset the pic16f87/88 differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during sleep wdt reset during normal operation wdt wake-up during sleep brown-out reset (bor) some registers are not affected in any reset condi- tion. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep, and brown-out reset (bor). they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. the to and pd bits are set or cleared differently in different reset situa- tions, as indicated in table 15-3. these bits are used in software to determine the nature of the reset. upon a por, bor, or wake-up from sleep, the cpu requires approximately 5-10 s to become ready for code execution. this delay runs in parallel with any other timers. see table 15-4 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 15-1. figure 15-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt intrc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 11-bit ripple counter reset enable ost enable pwrt sleep brown-out reset boren 31.25 khz
? 2003 microchip technology inc. preliminary ds30487b-page 133 pic16f87/88 15.3 mclr pic16f87/88 devices have a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. the behavior of the esd protection on the mclr pin has been altered from previous devices of this family. voltages applied to the pin, that exceed its specifica- tion, can result in both mclr and excessive current beyond the device specification during the esd event. the circuit, as shown in figure 15-2, is suggested. the ra5/mclr pin can be configured for mclr (default), or as an i/o pin (ra5). this is configured through the mclre bit in configuration word 1. figure 15-2: external power-on reset circuit (for slow v dd power-up) 15.4 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.2v-1.7v). to take advantage of the por, tie the mclr pin to v dd , as described in section 15.3 ?mclr ? . a maximum rise time for v dd is specified. see section 18.0 ?electrical characteristics? for details. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for more information, see application note, an607 ?power-up trouble shooting? (ds00607). 15.5 power-up timer (pwrt) the power-up timer (pwrt) of the pic16f87/88 is a counter that uses the intrc oscillator as the clock input. this yields a count of 72 ms. while the pwrt is counting, the device is held in reset. the power-up time delay depends on the intrc, and will vary from chip-to-chip due to temperature and process variation. see dc parameter #33 for details. the pwrt is enabled by clearing configuration bit pwrten . 15.6 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycles (from osc1 input) delay after the pwrt delay is over (if enabled). this helps to ensure that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset, or wake-up from sleep. 15.7 brown-out reset (bor) the configuration bit, boren, can enable or disable the brown-out reset circuit. if v dd falls below v bor (parameter d005, about 4v) for longer than t bor (parameter #35, about 100 s), the brown-out situation will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer (if enabled) will keep the device in reset for t pwrt (parameter #33, about 72 ms). if v dd should fall below v bor during t pwrt , the brown- out reset process will restart when v dd rises above v bor , with the power-up timer reset. unlike previous pic16 devices, the pwrt is no longer automatically enabled when the brown-out reset circuit is enabled. the pwrten and boren configuration bits are independent of each other. note: for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device?s electrical specification. 3: r1 = 1 k ? to 10 k ? will limit any current flow- ing into mclr from external capacitor c (0.1 f), in the event of mclr/ v pp pin break- down due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic16f87/88
pic16f87/88 ds30487b-page 134 preliminary ? 2003 microchip technology inc. 15.8 time-out sequence on power-up, the time-out sequence is as follows: the pwrt delay starts (if enabled) when a por occurs. then, ost starts counting 1024 oscillator cycles when pwrt ends (lp, xt, hs). when the ost ends, the device comes out of reset. if mclr is kept low long enough, all delays will expire. bringing mclr high will begin execution immediately. this is useful for testing purposes, or to synchronize more than one pic16f87/88 device operating in parallel. table 15-3 shows the reset conditions for the status, pcon and pc registers, while table 15-4 shows the reset conditions for all the registers. 15.9 power control/status register (pcon) the power control/status register, pcon, has two bits to indicate the type of reset that last occurred. bit0 is brown-out reset status bit, bor . bit bor is unknown on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bor cleared, indicating a brown-out reset occurred. when the brown-out reset is disabled, the state of the bor bit is unpredictable. bit1 is por (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. table 15-1: time-out in various situations table 15-2: status bits and their significance oscillator configuration power-up brown-out reset wake-up from sleep pwrte = 0 pwrte = 1 pwrte = 0 pwrte = 1 xt, hs, lp t pwrt + 1024 t osc 1024 t osc t pwrt + 1024 t osc 1024 t osc 1024 t osc extrc, intrc t pwrt 5-10 s (1) t pwrt 5-10 s (1) 5-10 s (1) t1osc ? ???5-10 s (1) note 1: cpu start-up is always invoked on por, bor and wake-up from sleep. the 5 s-10 s delay is based on a 1 mhz system clock. por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep legend: u = unchanged, x = unknown
? 2003 microchip technology inc. preliminary ds30487b-page 135 pic16f87/88 table 15-3: reset condition for special registers condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). table 15-4: initialization conditions for all registers register power-on reset, brown-out reset mclr reset, wdt reset wake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf n/a n/a n/a tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000h 0000h pc + 1 (2) status 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu porta (pic16f87) porta (pic16f88) xxxx 0000 xxx0 0000 uuuu 0000 uuu0 0000 uuuu uuuu uuuu uuuu portb (pic16f87) portb (pic16f87) xxxx xxxx 00xx xxxx uuuu uuuu 00uu uuuu uuuu uuuu uuuu uuuu pclath ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuuu (1) pir1 -000 0000 -000 0000 -uuu uuuu (1) pir2 00-0 ---- 00-0 ---- uu-u ---- (1) tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu t1con -000 0000 -uuu uuuu -uuu uuuu tmr2 0000 0000 0000 0000 uuuu uuuu t2con -000 0000 -000 0000 -uuu uuuu sspbuf xxxx xxxx uuuu uuuu uuuu uuuu sspcon 0000 0000 0000 0000 uuuu uuuu ccpr1l xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con --00 0000 --00 0000 --uu uuuu rcsta 0000 000x 0000 000x uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition, r = reserved, maintain clear note 1: one or more bits in intcon, pir1 and pr2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 15-3 for reset value for specific condition.
pic16f87/88 ds30487b-page 136 preliminary ? 2003 microchip technology inc. txreg 0000 0000 0000 0000 uuuu uuuu rcreg 0000 0000 0000 0000 uuuu uuuu adresh xxxx xxxx uuuu uuuu uuuu uuuu adcon0 0000 00-0 0000 00-0 uuuu uu-u option 1111 1111 1111 1111 uuuu uuuu trisa 1111 1111 1111 1111 uuuu uuuu trisb 1111 1111 1111 1111 uuuu uuuu pie1 -000 0000 -000 0000 -uuu uuuu pie2 00-0 ---- 00-0 ---- uu-u ---- pcon ---- --qq ---- --uu ---- --uu osccon -000 0000 -000 0000 -uuu uuuu osctune --00 0000 --00 0000 --uu uuuu pr2 1111 1111 1111 1111 1111 1111 sspadd 0000 0000 0000 0000 uuuu uuuu sspstat 0000 0000 0000 0000 uuuu uuuu txsta 0000 -010 0000 -010 uuuu -u1u spbrg 0000 0000 0000 0000 uuuu uuuu ansel -111 1111 -111 1111 -111 1111 cmcon 0000 0111 0000 0111 uuuu u111 cvrcon 000- 0000 000- 0000 uuu- uuuu wdtcon ---0 1000 ---0 1000 ---u uuuu adresl xxxx xxxx uuuu uuuu uuuu uuuu adcon1 0000 ---- 0000 ---- uuuu ---- eedata xxxx xxxx uuuu uuuu uuuu uuuu eeadr xxxx xxxx uuuu uuuu uuuu uuuu eedath --xx xxxx --uu uuuu --uu uuuu eeadrh ---- -xxx ---- -uuu ---- -uuu eecon1 x--x x000 u--x u000 u--u uuuu eecon2 ---- ---- ---- ---- ---- ---- table 15-4: initialization conditi ons for all registers (continued) register power-on reset, brown-out reset mclr reset, wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition, r = reserved, maintain clear note 1: one or more bits in intcon, pir1 and pr2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 15-3 for reset value for specific condition.
? 2003 microchip technology inc. preliminary ds30487b-page 137 pic16f87/88 figure 15-3: time-out sequence on power-up (mclr tied to v dd through pull-up resistor) figure 15-4: time-out sequence on power-up (mclr tied to v dd through rc network): case 1 figure 15-5: time-out sequence on power-up (mclr tied to v dd through rc network): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
pic16f87/88 ds30487b-page 138 preliminary ? 2003 microchip technology inc. figure 15-6: slow rise time (mclr tied to v dd through rc network) 15.10 interrupts the pic16f87/88 has up to 12 sources of interrupt. the interrupt control register (intcon) records indi- vidual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupt?s flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the ?return from interrupt? instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the special function register, pir1. the corresponding interrupt enable bits are contained in special function register, pie1, and the peripheral interrupt enable bit is contained in special function register, intcon. when an interrupt is serviced, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack, and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends on when the interrupt event occurs, relative to the current q cycle. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, peie bit or the gie bit. v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost note: individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit.
? 2003 microchip technology inc. preliminary ds30487b-page 139 pic16f87/88 figure 15-7: interrupt logic osfif osfie adif adie rcif rcie txif txie sspif sspie tmr2if tmr2ie tmr1if tmr1ie tmr0if tmr0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu eeif eeie ccp1if ccp1ie cmie cmif
pic16f87/88 ds30487b-page 140 preliminary ? 2003 microchip technology inc. 15.10.1 int interrupt external interrupt on the rb0/int pin is edge-triggered, either rising, if bit intedg (option<6>) is set, or fall- ing, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit, intf (intcon<1>), is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int inter- rupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global interrupt enable bit gie decides whether or not the processor branches to the interrupt vector, following wake-up. see section 15.13 ?power-down mode (sleep)? for details on sleep mode. 15.10.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set flag bit tmr0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit tmr0ie (intcon<5>), see section 6.0 ?timer0 module? . 15.10.3 portb intcon change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>), see section 3.2 ?eecon1 and eecon2 registers? . 15.11 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt (i.e., w, status registers). since the upper 16 bytes of each bank are common in the pic16f87/88 devices, temporary holding registers w_temp, status_temp, and pclath_temp should be placed in here. these 16 locations don?t require banking and therefore, make it easier for con- text save and restore. the same code shown in example 15-1 can be used. example 15-1: saving status, w, and pclath registers in ram movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using page 1 movwf pclath_temp ;save pclath into w clrf pclath ;page zero, regardless of current page : :(isr) ;(insert user code here) : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
? 2003 microchip technology inc. preliminary ds30487b-page 141 pic16f87/88 15.12 watchdog timer (wdt) for pic16f87/88 devices, the wdt has been modified from previous pic16 devices. the new wdt is code and functionally backward compatible with previous pic16 wdt modules, and allows the user to have a scaler value for the wdt and tmr0 at the same time. in addition, the wdt time-out value can be extended to 268 seconds, using the prescaler with the postscaler when psa is set to ? 1 ?. 15.12.1 wdt oscillator the wdt derives its time base from the 31.25 khz intrc. the value of wdtcon is ? ---0 1000 ? on all resets. this gives a nominal time base of 16.38 ms, which is compatible with the time base generated with previous pic16 microcontroller versions. a new prescaler has been added to the path between the internal rc and the multiplexors used to select the path for the wdt. this prescaler is 16 bits and can be programmed to divide the internal rc by 128 to 65536, giving the time base used for the wdt a nominal range of 1 ms to 2.097s. 15.12.2 wdt control the wdten bit is located in configuration word 1 and when this bit is set, the wdt runs continuously. the swdten bit is in the wdtcon register. when the wdten bit in the configuration word 1 register is set, the swdten bit has no effect. if wdten is clear, then the swdten bit can be used to enable and disable the wdt. setting the bit will enable it and clearing the bit will disable it. the psa and ps<2:0> bits (option_reg) have the same function as in previous versions of the pic16 family of microcontrollers. figure 15-8: watchdog timer block diagram note: when the ost is invoked, the wdt is held in reset, because the wdt ripple counter is used by the ost to perform the oscillator delay count. when the ost count has expired, the wdt will begin counting (if enabled). 31.25 khz psa 16-bit programmable prescaler wdt from tmr0 clock source postscaler 8 ps<2:0> psa wdt time-out to tmr0 wdtps<3:0> wdten from configuration word 1 1 0 0 swdten from wdtcon intrc clock
pic16f87/88 ds30487b-page 142 preliminary ? 2003 microchip technology inc. register 15-3: wdtcon register (address 105h) table 15-6: summary of watchdog timer registers table 15-5: prescaler/postscaler bit status conditions prescaler postscaler (psa = 1 ) wdten = 0 cleared cleared clrwdt command oscillator fail detected exit sleep + system clock = t1osc, extrc, intrc, extclk exit sleep + system clock = xt, hs, lp cleared at end of ost cleared at end of ost u-0 u-0 u-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 swdten (1) bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-1 wdtps<3:0>: watchdog timer period select bits bit prescale value rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16394 1010 = 1:32768 1011 = 1:65536 bit 0 swdten: software enable/disable for watchdog timer bit (1) 1 = wdt is turned on 0 = wdt is turned off note 1: if wdten configuration bit = 1 , then wdt is always enabled, irrespective of this con- trol bit. if wdten configuration bit = 0 , then it is possible to turn wdt on/off with this control bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 81h,181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 2007h configuration bits lvp boren mvclre f osc 2 pwrten wdten f osc 1 f osc 0 105h wdtcon ? ? ? wdtps3 wdtps2 wstps1 wdtps0 swdten legend: shaded cells are not used by the watchdog timer. note 1: see register 15-1 for operation of these bits.
? 2003 microchip technology inc. preliminary ds30487b-page 143 pic16f87/88 15.12.3 two-speed clock start-up mode two-speed start-up mode minimizes the latency between oscillator start-up and code execution that may be selected with the ieso (internal/external switch over) bit in configuration word 2. this mode is achieved by initially using the intrc for code execution until the primary oscillator is stable. if this mode is enabled, and any of the following condi- tions exist, the system will begin execution with the intrc oscillator. this results in almost immediate code execution with a minimum of delay. por and after the power-up timer has expired (if pwrten = 0 ), or following a wake-up from sleep, or a reset when running from t1osc or intrc (after a reset, scs<1:0> are always set to ? 00 ?). if the primary oscillator is configured to be anything other than xt, lp, or hs, then two-speed start-up mode is disabled, because the primary oscillator will not require any time to become stable after por, or an exit from sleep. if the ircf bits of the osccon register are configured to a non-zero value prior to entering sleep mode, the system clock frequency will come from the output of the intosc. the iofs bit in the osccon register will be clear until the intosc is stable. this will allow the user to determine when the internal oscillator can be used for time critical applications. checking the state of the osts bit will confirm whether the primary clock configuration is engaged. if not, the osts bit will remain clear. when the device is auto-configured in intrc mode fol- lowing a por or wake-up from sleep, the rules for entering other oscillator modes still apply, meaning the scs<1:0> bits in osccon can be modified before the ost time-out has occurred. this would allow the appli- cation to wake-up from sleep, perform a few instruc- tions using the intrc as the clock source and go back to sleep without waiting for the primary oscillator to become stable. 15.12.3.1 two-speed start-up mode sequence 1. wake-up from sleep, reset, or por. 2. oscon bits configured to run from intrc (31.25 khz). 3. instructions begin execution by intrc (31.25 khz). 4. ost enabled to count 1024 clock cycles. 5. ost timed out, wait for falling edge of intrc. 6. osts is set. 7. system clock held low for eight falling edges of new clock (lp, xt, or hs). 8. system clock is switched to primary source (lp, xt, or hs). the software may read the osts bit to determine when the switch over takes place so that any software timing edges can be adjusted. figure 15-9: two-speed start-up mode note: following any reset, the ircf bits are zeroed and the frequency selection is forced to 31.25 khz. the user can modify the ircf bits to select a higher internal oscillator frequency. note: executing a sleep instruction will abort the oscillator start-up time and will cause the osts bit to remain clear. q4 q1 q3 q4 q1 q2 osc1 sleep program pc 0000h intrc t ost q3 q4 osc2 osts system clock 0001h q1 q2 q3 q4 q1 q2 counter 0004h 0005h 0003h q1 q2 q3 q4 cpu start-up
pic16f87/88 ds30487b-page 144 preliminary ? 2003 microchip technology inc. 15.12.4 fail-safe option the fail-safe clock monitor (fscm) is designed to allow the device to continue to operate even in the event of an oscillator failure. figure 15-10: fscm block diagram the fscm function is enabled by setting the fcmen bit in configuration word 2. in the event of an oscillator failure, the fscm will gen- erate an oscillator fail interrupt and will switch the sys- tem clock over to the internal oscillator. the system will continue to come from the internal oscillator until the fail-safe condition is exited. the fail-safe condition is exited with either a reset, the execution of a sleep instruction or a write to the osccon register. the frequency of the internal oscillator will depend upon the value contained in the ircf bits. another clock source can be selected via the ircf and the scs bits of the osccon register. the fscm sample clock is generated by dividing the intrc clock by 64. this will allow enough time between fscm sample clocks for a system clock edge to occur. on the rising edge of the postscaled clock, the moni- toring latch (cm = 0 ) will be cleared. on a falling edge of the primary or secondary system clock, the monitor- ing latch will be set (cm = 1 ). in the event that a falling edge of the postscaled clock occurs, and the monitoring latch is not set, a clock failure has been detected. while in fail-safe mode, a reset will exit the fail- safe condition. if the primary clock source is config- ured for a crystal, the ost timer will wait for the 1024 clock cycles for the ost time-out, and the device will continue running from the internal oscillator until the ost is complete. a sleep instruction, or a write to the scs bits (where scs bits do not = 00 ), can be performed to put the device into a low-power mode. if reset occurs while in fail-safe mode and the pri- mary clock source is ec, or rc, then the device will immediately switch back to ec or rc mode. 15.12.4.1 fail-safe in low-power mode a write to the osccon register, or sleep instruction will end the fail-safe condition. the system clock will default to the source selected by the scs bits, which is either t1osc, intrc, or none (sleep mode). however, the fscm will continue to monitor the sys- tem clock. if the secondary clock fails, the device will immediately switch to the internal oscillator clock. if osfie is set, an interrupt will be generated. figure 15-11: fscm timing diagram peripheral intrc 64 s c q 31.25 khz (32 s) 488 hz (2.048 ms) clock monitor latch (cm) (edge-triggered) clock failure detected oscillator clock q note: two-speed start-up mode is automatically enabled when the fail-safe option is enabled. oscfif cm output system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test
? 2003 microchip technology inc. preliminary ds30487b-page 145 pic16f87/88 15.12.4.2 fscm and the watchdog timer when a clock failure is detected, scs<1:0> will be forced to ? 10 ?, which will reset the wdt (if enabled). 15.12.4.3 por or wake from sleep the fscm is designed to detect oscillator failure at any point after the device has exited power-on reset (por) or low-power sleep mode. when the primary system clock is ec, rc or intrc modes, monitoring can begin immediately following these events. for oscillator modes involving a crystal or resonator (hs, lp, or xt), the situation is somewhat different. since the oscillator may require a start-up time consid- erably longer than the fscm sample clock time, a false clock failure may be detected. to prevent this, the inter- nal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the ost timer has timed out). this is identical to two-speed start-up mode. once the primary clock is stable, the intrc returns to its role as the fscm source. 15.12.4.4 example fail-safe conditions 1. conditions: the device is clocked from a crystal, crystal operation fails and then sleep mode is entered. osts = 0 scs = 00 osfif = 1 user action: sleep mode will exit the fail-safe condition. therefore, if the user code did not handle the detected fail-safe prior to the sleep command, then upon wake-up, the device will try to start the crystal that failed and a fail-safe condition will not be detected. monitoring the osts bit will determine if the crystal is operating. the user should not enter sleep mode without handling the fail-safe condition first. 2. conditions: after a por (power-on reset), the device is running in two-speed start-up mode. the crys- tal fails before the ost has expired. if a crystal fails during the ost period, a fail-safe condition will not be detected (osfif will not get set). osts = 0 scs = 00 osfif = 0 user action: check the osts bit. if it?s clear and the ost should have expired at this point, then the user can assume the crystal has failed. the user should change the scs bit to cause a clock switch which will also release the 10-bit ripple counter for wdt operation (if enabled). 3. conditions: the device is clocked from a crystal during normal operation and it fails. osts = 0 scs = 00 osfif = 1 user action: clear the osfif bit. configure the scs bits for a clock switch and the fail-safe condition will be cleared. later, if the user decides to, the crystal can be re-tried for operation. if this is done, the osts bit should be monitored to determine if the crystal operates. 15.13 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low, or high-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should also be considered. the mclr pin must be at a logic high level (v ihmc ). note: the same logic that prevents false oscilla- tor failure interrupts on port or wake from sleep, will also prevent the detec- tion of the oscillator?s failure to start at all following these events. this can be avoided by monitoring the osts bit and using a timing routine to determine if the oscillator is taking too long to start. even so, no oscillator failure interrupt will be flagged.
pic16f87/88 ds30487b-page 146 preliminary ? 2003 microchip technology inc. 15.13.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or a peripheral interrupt. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a ?wake-up?. the to and pd bits in the status register can be used to determine the cause of the device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred and caused wake-up. the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ccp capture mode interrupt. 3. special event trigger (timer1 in asynchronous mode using an external clock). 4. ssp (start/stop) bit detect interrupt. 5. ssp transmit or receive in slave mode (spi/i 2 c). 6. a/d conversion (when a/d clock source is rc). 7. eeprom write operation completion. 8. comparator output changes state. 9. usart rx or tx (synchronous slave mode). other peripherals cannot generate interrupts, since during sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up occurs regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt address (0004h). in cases where the execu- tion of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 15.13.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop . therefore, the wdt and wdt prescaler and postscaler (if enabled) will not be cleared, the to bit will not be set and the pd bit will not be cleared. if the interrupt occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt prescaler and postscaler (if enabled) will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruction should be executed before a sleep instruction. figure 15-12: wake-up from sleep through interrupt (1) q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clko (4) int pin intf flag (intcon<1>) gie bit (3) (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (drawing not to scale). this delay will not be there for rc osc mode. 3: gie = 1 assumed. in this case, after wake-up, th e processor jumps to the interrupt routine. if gie = 0 , execution will continue in-line. 4: clko is not available in these osc modes, but shown here for timing reference.
? 2003 microchip technology inc. preliminary ds30487b-page 147 pic16f87/88 15.14 in-circuit debugger when the debug bit in the configuration word is pro- grammed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging func- tions when used with mplab ? icd. when the micro- controller has this feature enabled, some of the resources are not available for general use. table 15-7 shows which features are consumed by the background debugger. table 15-7: debugger resources to use the in-circuit debugger function of the micro- controller, the design must implement in-circuit serial programming connections to mclr /v pp , v dd , gnd, rb7 and rb6. this will interface to the in-circuit debugger module available from microchip, or one of the third party development tool companies. 15.15 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 15.16 id locations four memory locations (2000h - 2003h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are read- able and writable during program/verify. it is recom- mended that only the four least significant bits of the id location are used. 15.17 in-circuit serial programming pic16f87/88 microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage (see figure 15-13 for an example). this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. for more information on serial programming, please refer to the pic16f87/88 programming specification (ds39607). figure 15-13: typical in-circuit serial programming connection i/o pins rb6, rb7 stack 1 level program memory address 0000h must be nop last 100h words data memory 0x070 (0x0f0, 0x170, 0x1f0) 0x1eb-0x1ef external connector signals to normal connections to n o r m a l connections pic16f87/88 v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd * * * * * isolation devices (as required). ? rb3 only used in lvp mode. rb3 ? rb3/pgm
pic16f87/88 ds30487b-page 148 preliminary ? 2003 microchip technology inc. 15.18 low-voltage icsp programming the lvp bit of the configuration word enables low- voltage icsp programming. this mode allows the microcontroller to be programmed via icsp using a v dd source in the operating voltage range. this only means that v pp does not have to be brought to v ihh , but can instead be left at the normal operating voltage. in this mode, the rb3/pgm pin is dedicated to the pro- gramming function and ceases to be a general purpose i/o pin. if low-voltage programming mode is not used, the lvp bit can be programmed to a ? 0 ? and rb3/pgm becomes a digital i/o pin. however, the lvp bit may only be pro- grammed when programming mode is entered with v ihh on mclr . the lvp bit can only be changed when using high voltage on mclr . it should be noted that once the lvp bit is programmed to ? 0 ?, only the high-voltage programming mode is available and only this mode can be used to program the device. when using low-voltage icsp, the part must be sup- plied at 4.5v to 5.5v if a bulk erase will be executed. this includes reprogramming of the code protect bits from an on-state to an off-state. for all other cases of low- voltage icsp, the part may be programmed at the nor- mal operating voltage. this means calibration values, unique user ids, or user code can be reprogrammed or added. the following lvp steps assume the lvp bit is set in the configuration register. 1. apply v dd to the v dd pin. 2. drive mclr low. 3. apply v dd to the rb3/pgm pin. 4. apply v dd to the mclr pin. 5. follow with the associated programming steps. note 1: the high-voltage programming mode is always available, regardless of the state of the lvp bit, by applying v ihh to the mclr pin. 2: while in low-voltage icsp mode (lvp = 1 ), the rb3 pin can no longer be used as a general purpose i/o pin. 3: when using low-voltage icsp program- ming (lvp) and the pull-ups on portb are enabled, bit 3 in the trisb register must be cleared to disable the pull-up on rb3 and ensure the proper operation of the device. 4: rb3 should not be allowed to float if lvp is enabled. an external pull-down device should be used to default the device to normal operating mode. if rb3 floats high, the pic16f87/88 device will enter programming mode. 5: lvp mode is enabled by default on all devices shipped from microchip. it can be disabled by clearing the lvp bit in the config register. 6: disabling lvp will provide maximum compatibility to other pic16cxxx devices.
? 2003 microchip technology inc. preliminary ds30487b-page 149 pic16f87/88 16.0 instruction set summary the pic16 instruction set is highly orthogonal and is comprised of three basic categories: byte-oriented operations bit-oriented operations literal and control operations each pic16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. the formats for each of the catego- ries are presented in figure 16-1, while the various opcode fields are summarized in table 16-1. table 16-2 lists the instructions recognized by the mpasm tm assembler. a complete description of each instruction is also available in the picmicro ? mid-range mcu family reference manual (ds33023). for byte-oriented instructions, ?f? represents a file reg- ister designator and ?d? represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the w register. if ?d? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator, which selects the bit affected by the opera- tion, while ?f? represents the address of the file in which the bit is located. for literal and control operations, ?k? represents an eight or eleven-bit constant or literal value one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a normal instruction execution time of 1 s. all instructions are executed within a single instruction cycle, unless a con- ditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the exe- cution takes two instruction cycles, with the second cycle executed as a nop . all instruction examples use the format ? 0xhh ? to repre- sent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 16.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. for example, a ? clrf portb ? instruction will read portb, clear all the data bits, then write the result back to portb. this example would have the unin- tended result that the condition that sets the rbif flag would be cleared. table 16-1: opcode field descriptions figure 16-1: general format for instructions note: to maintain upward compatibility with future pic16f87/88 products, do not use the option and tris instructions. field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1 : store result in file register f. default is d = 1. pc program counter to time-out bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16f87/88 ds30487b-page 150 preliminary ? 2003 microchip technology inc. table 16-2: pic16f87/88 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself (e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for exam ple, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tm r0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instructi on requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the picmicro ? mid-range mcu family reference manual (ds33023).
? 2003 microchip technology inc. preliminary ds30487b-page 151 pic16f87/88 16.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? = 0 , the result is stored in the w register. if ?d? = 1 , the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register ?f?. if ?d? = 0 , the result is stored in the w register. if ?d? = 1 , the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set.
pic16f87/88 ds30487b-page 152 preliminary ? 2003 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? = 0 , the next instruction is executed. if bit ?b? = 1 , then the next instruction is discarded and a nop is executed instead, making this a 2t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? = 1 , the next instruction is executed. if bit ?b?, in register ?f?, = 0 , the next instruction is discarded, and a nop is executed instead, making this a 2 t cy instruction. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc) + 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven-bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set.
? 2003 microchip technology inc. preliminary ds30487b-page 153 pic16f87/88 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? = 0 , the result is stored in w. if ?d? = 1 , the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register ?f?. if ?d? = 0 , the result is stored in the w register. if ?d? = 1 , the result is stored back in register ?f?. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? = 0 , the result is placed in the w register. if ?d? = 1 , the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? = 0 , the result is placed in the w register. if ?d? = 1 , the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? = 0 , the result is placed in the w register. if ?d? = 1 , the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2 t cy instruction.
pic16f87/88 ds30487b-page 154 preliminary ? 2003 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or?d with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? = 0 , the result is placed in the w register. if ?d? = 1 , the result is placed back in register ?f?. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register ?f? are moved to a destination dependant upon the status of ?d?. if ?d? = 0 , the destination is w register. if ?d? = 1 , the destination is file register ?f? itself. ?d? = 1 is useful to test a file register, since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the don?t cares will assemble as ? 0 ?s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none description: move data from w register to register ?f?. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation.
? 2003 microchip technology inc. preliminary ds30487b-page 155 pic16f87/88 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? = 0 , the result is placed in the w register. if ?d? = 1 , the result is stored back in register ?f?. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? = 0 , the result is placed in the w register. if ?d? = 1 , the result is placed back in register ?f?. sleep syntax: [ label ]sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c register f c
pic16f87/88 ds30487b-page 156 preliminary ? 2003 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z description: the w register is subtracted (2?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? = 0 , the result is stored in the w register. if ?d? = 1 , the result is stored back in register ?f?. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? = 0 , the result is placed in w register. if ?d? = 1 , the result is placed in register ?f?. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? = 0 , the result is stored in the w register. if ?d? = 1 , the result is stored back in register ?f?.
? 2003 microchip technology inc. preliminary ds30487b-page157 pic16f87/88 17.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer low-cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? - picdem msc -microid ? -can - powersmart ? -analog 17.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - absolute listing file (mixed assembly and c) - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 17.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process
pic16f87/88 ds30487b-page 158 preliminary ? 2003 microchip technology inc. 17.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 17.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of pre-compiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 17.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command- line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties, and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been vali- dated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, time- keeping, and math functions (trigonometric, exponen- tial and hyperbolic). the compiler provides symbolic information for high level source debugging with the mplab ide. 17.6 mplab asm30 assembler, linker, and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire dspic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 17.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 17.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high-speed simulator is designed to debug, analyze and optimize time intensive dsp routines.
? 2003 microchip technology inc. preliminary ds30487b-page159 pic16f87/88 17.9 mplab ice 2000 high-performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 17.10 mplab ice 4000 high-performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory, and the ability to view variables in real time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 17.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debug- ging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 17.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, and program picmicro devices without a pc connection. it can also set code protection in this mode. 17.13 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant.
pic16f87/88 ds30487b-page 160 preliminary ? 2003 microchip technology inc. 17.14 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer, or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a pro- totype area extends the circuitry for additional applica- tion components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 17.15 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface, and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 17.16 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18-, 28-, and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds, and sample pic18f452 and pic16f877 flash microcontrollers. 17.17 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 17.18 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8-, 14-, and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 fam- ily of microcontrollers. picdem 4 is intended to show- case the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low-power operation with the supercapacitor circuit, and jumpers allow on-board hardware to be disabled to eliminate current draw in this mode. included on the demo board are provisions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for program- ming via icsp and development with mplab icd 2, 2x16 liquid crystal display, pcb footprints for h-bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a prototyping area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide. 17.19 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is included. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion.
? 2003 microchip technology inc. preliminary ds30487b-page161 pic16f87/88 17.20 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/de-multiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 17.21 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 17.22 pickit tm 1 flash starter kit a complete "development system in a box", the pickit flash starter kit includes a convenient multi-section board for programming, evaluation, and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user's guide (on cd rom), pickit 1 tutorial software and code for vari- ous applications. also included are mplab ? ide (inte- grated development environment) software, software and hardware "tips 'n tricks for 8-pin flash pic ? microcontrollers" handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 17.23 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 17.24 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. k ee l oq evaluation and programming tools for microchip?s hcs secure data products can developers kit for automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high-power ir driver, delta sigma adc, and flow rate sensor check the microchip web page and the latest product line card for the complete list of demonstration and evaluation kits.
pic16f87/88 ds30487b-page 162 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 163 pic16f87/88 18.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............-55c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd and m clr ) ................................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................ -0.3 to +7.5v voltage on mclr with respect to v ss (note 2) .............................................................................................-0.3 to +14v total power dissipation (note 1) ............................................................................................................................... ...1w maximum current out of v ss pin ........................................................................................................................... 200 ma maximum current into v dd pin ........................................................................................................................... ...200 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta ........................................................................................................................10 0 ma maximum current sourced by porta............................................................................................... ....................100 ma maximum current sunk by portb........................................................................................................................10 0 ma maximum current sourced by portb ............................................................................................... ...................100 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes at the mclr pin may cause latch-up. a series resistor of greater than 1 k ? should be used to pull mclr to v dd , rather than tying the pin directly to v dd . ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16f87/88 ds30487b-page 164 preliminary ? 2003 microchip technology inc. figure 18-1: pic16f87/88 voltage-frequency graph figure 18-2: pic16lf87/88 voltage-frequency graph frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 20 mhz 5.0v 3.5v 3.0v 2.5v 16 mhz frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 5.0v 3.5v 3.0v 2.5v f max = (12 mhz/v) (v ddappmin ? 2.5v) + 4 mhz note 1: v ddappmin is the minimum voltage of the picmicro ? device in the application. 4 mhz 10 mhz note 2: f max has a maximum frequency of 10 mhz.
? 2003 microchip technology inc. preliminary ds30487b-page 165 pic16f87/88 18.1 dc characteristics: supply voltage pic16f87/88 (industrial) pic16lf87/88 (industrial) pic16lf87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min typ max units conditions v dd supply voltage d001 pic16lf87/88 2.0 ? 5.5 v hs, xt, rc and lp osc mode d001 pic16f87/88 4.0 ? 5.5 v d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd start voltage to ensure internal power-on reset signal ? ? 0.7 v see section 15.4 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 15.4 ?power-on reset (por)? for details v bor brown-out reset voltage d005 pic16lf87/88 3.65 ? 4.35 v d005 pic16f87/88 3.65 ? 4.35 v f max = 14 mhz (2) legend: shading of rows is to assist in readability of the table. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
pic16f87/88 ds30487b-page 166 preliminary ? 2003 microchip technology inc. 18.2 dc characteristics: power-down and supply current pic16f87/88 (industrial) pic16lf87/88 (industrial) pic16lf87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions power-down current (i pd ) (1) pic16lf87/88 0.1 0.4 a -40c 0.1 0.4 a 25c v dd = 2.0v 0.4 1.5 a 85c pic16lf87/88 0.3 0.5 a -40c 0.3 0.5 a 25c v dd = 3.0v 0.7 1.7 a 85c all devices 0.6 1.0 a -40c 0.6 1.0 a 25c v dd = 5.0v 1.2 5.0 a 85c legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
? 2003 microchip technology inc. preliminary ds30487b-page 167 pic16f87/88 supply current (i dd ) (2,3) pic16lf87/88 9 20 a -40c f osc = 32 kh z (lp oscillator) 715 a 25c v dd = 2.0v 715 a 85c pic16lf87/88 16 30 a -40c 14 25 a 25c v dd = 3.0v 14 25 a 85c all devices 32 40 a -40c 26 35 a 25c v dd = 5.0v 26 35 a 85c pic16lf87/88 72 95 a -40c f osc = 1 mh z (rc oscillator) (3) 76 90 a 25c v dd = 2.0v 76 90 a 85c pic16lf87/88 138 175 a -40c 136 170 a 25c v dd = 3.0v 136 170 a 85c all devices 310 380 a -40c 290 360 a 25c v dd = 5.0v 280 360 a 85c pic16lf87/88 270 315 a -40c f osc = 4 mhz (rc oscillator) (3) 280 310 a 25c v dd = 2.0v 285 310 a 85c pic16lf87/88 460 610 a -40c 450 600 a 25c v dd = 3.0v 450 600 a 85c all devices 900 1060 a -40c 890 1050 a 25c v dd = 5.0v 890 1050 a 85c 18.2 dc characteristics: power-down and supply current pic16f87/88 (industrial) pic16lf87/88 (industrial) (continued) pic16lf87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
pic16f87/88 ds30487b-page 168 preliminary ? 2003 microchip technology inc. supply current (i dd ) (2,3) all devices 1.8 2.3 ma -40c f osc = 20 mh z (hs oscillator) 1.6 2.2 ma 25c v dd = 4.0v 1.3 2.2 ma 85c all devices 3.0 4.2 ma -40c 2.5 4.0 ma 25c v dd = 5.0v 2.5 4.0 ma 85c 18.2 dc characteristics: power-down and supply current pic16f87/88 (industrial) pic16lf87/88 (industrial) (continued) pic16lf87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
? 2003 microchip technology inc. preliminary ds30487b-page 169 pic16f87/88 supply current (i dd ) (2,3) pic16lf87/88 8 20 a -40c f osc = 31.25 khz ( rc_run mode, internal rc oscillator) 715 a 25c v dd = 2.0v 715 a 85c pic16lf87/88 16 30 a -40c 14 25 a 25c v dd = 3.0v 14 25 a 85c all devices 32 40 a -40c 29 35 a 25c v dd = 5.0v 29 35 a 85c pic16lf87/88 132 160 a -40c f osc = 1 mhz ( rc_run mode, internal rc oscillator) 126 155 a 25c v dd = 2.0v 126 155 a 85c pic16lf87/88 260 310 a -40c 230 300 a 25c v dd = 3.0v 230 300 a 85c all devices 560 690 a -40c 500 650 a 25c v dd = 5.0v 500 650 a 85c pic16lf87/88 310 420 a -40c f osc = 4 mhz ( rc_run mode, internal rc oscillator) 300 410 a 25c v dd = 2.0v 300 410 a 85c pic16lf87/88 550 650 a -40c 530 620 a 25c v dd = 3.0v 530 620 a 85c all devices 1.2 1.5 ma -40c 1.1 1.4 ma 25c v dd = 5.0v 1.1 1.4 ma 85c 18.2 dc characteristics: power-down and supply current pic16f87/88 (industrial) pic16lf87/88 (industrial) (continued) pic16lf87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
pic16f87/88 ds30487b-page 170 preliminary ? 2003 microchip technology inc. supply current (i dd ) (2,3) pic16lf87/88 .950 1.3 ma -40c f osc = 8 mhz ( rc_run mode, internal rc oscillator) .930 1.2 ma 25c v dd = 3.0v .930 1.2 ma 85c all devices 1.8 3.0 ma -40c 1.7 2.8 ma 25c v dd = 5.0v 1.7 2.8 ma 85c pic16lf87/88 9 13 a -10c f osc = 32 khz ( sec_run mode, timer1 as clock) 914 a 25c v dd = 2.0v 11 16 a 70c pic16lf87/88 12 34 a -10c 12 31 a 25c v dd = 3.0v 14 28 a 70c all devices 20 72 a -10c 20 65 a 25c v dd = 5.0v 25 59 a 70c 18.2 dc characteristics: power-down and supply current pic16f87/88 (industrial) pic16lf87/88 (industrial) (continued) pic16lf87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
? 2003 microchip technology inc. preliminary ds30487b-page 171 pic16f87/88 module differential currents ( ? i wdt , ? i bor , ? i lvd , ? i oscb , ? i ad ) d022 ( ? i wdt ) watchdog timer 1.5 3.8 a -40c 2.2 3.8 a 25c v dd = 2.0v 2.7 4.0 a 85c 2.3 4.6 a -40c 2.7 4.6 a 25c v dd = 3.0v 3.1 4.8 a 85c 3.0 10.0 a -40c 3.3 10.0 a 25c v dd = 5.0v 3.9 13.0 a 85c d022a ( ? i bor ) brown-out reset 40 60 a-40 c to +85 c v dd = 5.0v d025 ( ? i oscb ) timer1 oscillator 1.7 2.3 a -40c 32 khz on timer1 1.8 2.3 a 25c v dd = 2.0v 2.0 2.3 a 85c 2.2 3.8 a -40c 2.6 3.8 a 25c v dd = 3.0v 2.9 3.8 a 85c 3.0 6.0 a -40c 3.2 6.0 a 25c v dd = 5.0v 3.4 7.0 a 85c d026 ( ? i ad ) a/d converter 0.001 2.0 a-40 c to +85 c v dd = 2.0v a/d on, not converting 0.001 2.0 a-40 c to +85 c v dd = 3.0v 0.003 2.0 a-40 c to +85 c v dd = 5.0v 18.2 dc characteristics: power-down and supply current pic16f87/88 (industrial) pic16lf87/88 (industrial) (continued) pic16lf87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
pic16f87/88 ds30487b-page 172 preliminary ? 2003 microchip technology inc. 18.3 dc characteristics: internal rc accuracy pic16f87/88 (industrial) pic16lf87/88 (industrial) pic16lf87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f87/88 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device min typ max units conditions intosc accuracy @ freq = 8 mhz, 4 mhz, 2 mhz, 1 mhz, 500 khz, 250 khz, 125 khz (1) pic16lf87/88 -2 1 2 % 25c v dd = 2.7-3.3v -5 ? 5 % -10c - +85c v dd = 2.7-3.3v -10 ? 10 % -40c - +85c v dd = 2.7-3.3v pic16f87/88 -2 1 2 % 25c v dd = 4.5-5.5v -5 ? 5 % -10c - +85c v dd = 4.5-5.5v -10 ? 10 % -40c - +85c v dd = 4.5-5.5v intrc accuracy @ freq = 31 khz (2) pic16lf87/88 26.562 ? 35.938 khz -40c - +85c v dd = 2.7-3.3v pic16f87/88 26.562 ? 35.938 khz -40c - +85c v dd = 4.5-5.5v legend: shading of rows is to assist in readability of the table. note 1: frequency calibrated at 25c. osctune register can be used to compensate for temperature drift. 2: intrc frequency after calibration.
? 2003 microchip technology inc. preliminary ds30487b-page 173 pic16f87/88 18.4 dc characteristics: pic16f87/88 (industrial, extended) pic16lf87/88 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc specification, section 18.1 ?dc characteristics: supply voltage? . param no. sym characteristic min typ? max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss ?0.15 v dd v for entire v dd range d030a v ss ?0.8v v4.5v v dd 5.5v d031 with schmitt trigger buffer v ss ? 0.2 v dd v d032 mclr , osc1 (in rc mode) v ss ? 0.2 v dd v (note 1) d033 osc1 (in xt and lp mode) v ss ?0.3v v osc1 (in hs mode) v ss ? 0.3 v dd v ports rb1 and rb4: d034 with schmitt trigger buffer v ss ? 0.3 v dd v for entire v dd range v ih input high voltage i/o ports: d040 with ttl buffer 2.0 ? v dd v4.5v v dd 5.5v d040a 0.25 v dd + 0.8v ? v dd v for entire v dd range d041 with schmitt trigger buffer 0.8 v dd ?v dd v for entire v dd range d042 mclr 0.8 v dd ?v dd v d042a osc1 (in xt and lp mode) 1.6v ? v dd v osc1 (in hs mode) 0.7 v dd ?v dd v d043 osc1 (in rc mode) 0.9 v dd ?v dd v (note 1) ports rb1 and rb4: d044 with schmitt trigger buffer 0.7 v dd ?v dd v for entire v dd range d070 i purb portb weak pull-up current 50 250 400 av dd = 5v, v pin = v ss i il input leakage current (notes 2, 3) d060 i/o ports ? ? 1 avss v pin v dd , pin at high-impedance d061 mclr ??5 avss v pin v dd d063 osc1 ? ? 5 avss v pin v dd , xt, hs and lp osc configuration * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic16f87/88 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage cu rrent may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16f87/88 ds30487b-page 174 preliminary ? 2003 microchip technology inc. v ol output low voltage d080 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clko (rc osc configuration) ??0.6vi ol = 1.6 ma, v dd = 4.5v, -40 c to +125 c v oh output high voltage d090 i/o ports (note 3) v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clko (rc osc configuration) v dd ? 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, -40 c to +125 c capacitive loading specs on output pins d100 c osc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) ??50pf d102 c b scl, sda in i 2 c mode ??400pf data eeprom memory d120 e d endurance 100k 10k 1m 100k ? ? e/w e/w -40 c to 85 c +85 c to +125 c d121 v drw v dd for read/write v min ? 5.5 v using eecon to read/write, v min = min. operating voltage d122 t dew erase/write cycle time ? 4 8 ms program flash memory d130 e p endurance 10k 1k 100k 10k ? ? e/w e/w -40 c to 85 c +85 c to +125 c d131 v pr v dd for read v min ?5.5 v d132a v dd for erase/write v min ? 5.5 v using eecon to read/write, v min = min. operating voltage d133 t pe erase cycle time ? 2 4 ms d134 t pw write cycle time ? 2 4 ms 18.4 dc characteristics: pic16f87/88 (industrial, extended) pic16lf87/88 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc specification, section 18.1 ?dc characteristics: supply voltage? . param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic16f87/88 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage cu rrent may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 2003 microchip technology inc. preliminary ds30487b-page 175 pic16f87/88 table 18-1: comparator specifications table 18-2: voltage reference specifications operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c, unless otherwise stated. param no. characteristics sym min typ max units comments d300 input offset voltage v ioff ? 5.0 10mv d301 input common mode voltage* v icm 0-v dd ? 1.5 v d302 common mode rejection ratio* cmrr 55 - ? db 300 300a response time (1)* t resp ?150400 600 ns ns pic16f87/88 pic16lf87/88 301 comparator mode change to output valid* t mc 2 ov ?? 10 s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2 while the other input transitions from v ss to v dd . operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c, unless otherwise stated. spec no. characteristics sym min typ max units comments d310 resolution v res v dd /24 ? v dd /32 lsb d311 absolute accuracy vr aa ? ? ? ? 1/4 1/2 lsb lsb low range (vrr = 1 ) high range (vrr = 0 ) d312 unit resistor value (r)* vr ur ?2k? ? 310 settling time (1) * t set ? ? 10 s * these parameters are characterized but not tested. note 1: settling time measured while vrr = 1 and vr<3:0> transitions from ? 0000 ? to ? 1111 ?.
pic16f87/88 ds30487b-page 176 preliminary ? 2003 microchip technology inc. 18.5 timing parameter symbology the timing parameter symbols have been created using one of the following formats: figure 18-3: load conditions 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2, but including portd and porte outputs as ports 15 pf for osc2 output load condition 1 load condition 2
? 2003 microchip technology inc. preliminary ds30487b-page 177 pic16f87/88 figure 18-4: external clock timing osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 18-3: external clock timing requirements parameter no. sym characteristic min typ? max units conditions f osc external clki frequency (note 1) dc ? 1 mhz xt and rc osc mode dc ? 20 mhz hs osc mode dc ? 32 khz lp osc mode oscillator frequency (note 1) dc ? 4 mhz rc osc mode 0.1 ? 4 mhz xt osc mode 4 5 ? ? 20 200 mhz khz hs osc mode lp osc mode 1t osc external clki period (note 1) 1000 ? ? ns xt and rc osc mode 50 ? ? ns hs osc mode 5 ? ? ms lp osc mode oscillator period (note 1) 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 250 ns hs osc mode 5 ? ? ms lp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3 tosl, to sh external clock in (osc1) high or low time 500 ? ? ns xt oscillator 2.5 ? ? ms lp oscillator 15 ? ? ns hs oscillator 4tosr, to sf external clock in (osc1) rise or fall time ? ? 25 ns xt oscillator ? ? 50 ns lp oscillator ? ? 15 ns hs oscillator ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. exceeding these specified limits may result in an unstable oscillator oper- ation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices.
pic16f87/88 ds30487b-page 178 preliminary ? 2003 microchip technology inc. figure 18-5: clko and i/o timing table 18-4: clko and i/o timing requirements note: refer to figure 18-3 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. symbol characteristic min typ? max units conditions 10* tosh2ckl osc1 to clko ? 75 200 ns (note 1) 11* tosh2ckh osc1 to clko ? 75 200 ns (note 1) 12* tckr clko rise time ? 35 100 ns (note 1) 13* tckf clko fall time ? 35 100 ns (note 1) 14* tckl2iov clko to port out valid ? ? 0.5 t cy + 20 ns (note 1) 15* tiov2ckh port in valid before clko t osc + 200 ? ? ns (note 1) 16* tckh2ioi port in hold after clko 0??ns (note 1) 17* tosh2iov osc1 (q1 cycle) to port out valid ? 100 255 ns 18* tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) pic16 f 87/88 100 ? ? ns pic16 lf 87/88 200 ? ? ns 19* tiov2osh port input valid to osc1 (i/o in setup time) 0 ? ? ns 20* t io r port output rise time pic16 f 87/88 ? 10 40 ns pic16 lf 87/88 ? ? 145 ns 21* t io f port output fall time pic16 f 87/88 ? 10 40 ns pic16 lf 87/88 ? ? 145 ns 22??* t inp int pin high or low time t cy ??ns 23??* t rbp rb7:rb4 change int high or low time t cy ??ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clko output is 4 x t osc .
? 2003 microchip technology inc. preliminary ds30487b-page 179 pic16f87/88 figure 18-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 18-7: brown-out reset timing table 18-5: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 18-3 for load conditions. v dd v bor 35 parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 ? ? sv dd = 5v, -40c to +85c 31* t wdt watchdog timer time-out period (16-bit prescaler = 0100 and no postscaler) tbd 16 tbd ms v dd = 5v, -40c to +85c 32 t ost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33* t pwrt power-up timer period tbd 72 tbd ms v dd = 5v, -40c to +85c 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.1 s 35 t bor brown-out reset pulse width 100 ? ? sv dd v bor (d005) * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested.
pic16f87/88 ds30487b-page 180 preliminary ? 2003 microchip technology inc. figure 18-8: timer0 and timer1 external clock timings table 18-6: timer0 and timer1 external clock requirements param no. symbol characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 41* tt0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 42* tt0p t0cki period no prescaler t cy + 40 ? ? ns with prescaler greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5 t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 f 87/88 15 ? ? ns pic16 lf 87/88 25 ? ? ns asynchronous pic16 f 87/88 30 ? ? ns pic16 lf 87/88 50 ? ? ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5 t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 f 87/88 15 ? ? ns pic16 lf 87/88 25 ? ? ns asynchronous pic16 f 87/88 30 ? ? ns pic16 lf 87/88 50 ? ? ns 47* tt1p t1cki input period synchronous pic16 f 87/88 greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) pic16 lf 87/88 greater of: 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16 f 87/88 60 ? ? ns pic16 lf 87/88 100 ? ? ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 32.768 khz 48 tckeztmr1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note: refer to figure 18-3 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rb6/t1oso/t1cki tmr0 or tmr1
? 2003 microchip technology inc. preliminary ds30487b-page 181 pic16f87/88 figure 18-9: capture/compare/pwm timings (ccp1) table 18-7: capture/compare/pwm requirements (ccp1) note: refer to figure 18-3 for load conditions. ccp1 (capture mode) 50 51 52 53 54 ccp1 (compare or pwm mode) param no. symbol characteristic min typ? max units conditions 50* tccl ccp1 input low time no prescaler 0.5 t cy + 20 ? ? ns with prescaler pic16 f 87/88 10 ? ? ns pic16 lf 87/88 20 ? ? ns 51* tcch ccp1 input high time no prescaler 0.5 t cy + 20 ? ? ns with prescaler pic16 f 87/88 10 ? ? ns pic16 lf 87/88 20 ? ? ns 52* tccp ccp1 input period 3 t cy + 40 n ? ? ns n = prescale value (1,4 or 16) 53* tccr ccp1 output rise time pic16 f 87/88 ? 10 25 ns pic16 lf 87/88 ? 25 50 ns 54* tccf ccp1 output fall time pic16 f 87/88 ? 10 25 ns pic16 lf 87/88 ? 25 45 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16f87/88 ds30487b-page 182 preliminary ? 2003 microchip technology inc. figure 18-10: spi master mode timing (cke = 0 , smp = 0 ) figure 18-11: spi master mode timing (cke = 1 , smp = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 18-3 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 18-3 for load conditions.
? 2003 microchip technology inc. preliminary ds30487b-page 183 pic16f87/88 figure 18-12: spi slave mode timing (cke = 0 ) figure 18-13: spi slave mode timing (cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in 83 note: refer to figure 18-3 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit 6 - - - - - -1 lsb 77 msb in bit 6 - - - -1 lsb in 80 83 note: refer to figure 18-3 for load conditions.
pic16f87/88 ds30487b-page 184 preliminary ? 2003 microchip technology inc. table 18-8: spi mode requirements figure 18-14: i 2 c bus start/stop bits timing param no. symbol characteristic min typ? max units conditions 70* tssl2sch, tssl2scl ss to sck or sck input t cy ?? ns 71* tsch sck input high time (slave mode) t cy + 20 ? ? ns 72* tscl sck input low time (slave mode) t cy + 20 ? ? ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ? ns 74* tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ? ns 75* tdor sdo data output rise time pic16 f 87/88 pic16 lf 87/88 ? ? 10 25 25 50 ns ns 76* tdof sdo data output fall time ? 10 25 ns 77* tssh2doz ss to sdo output high-impedance 10 ? 50 ns 78* tscr sck output rise time (master mode) pic16 f 87/88 pic16 lf 87/88 ? ? 10 25 25 50 ns ns 79* tscf sck output fall time (master mode) ? 10 25 ns 80* tsch2dov, tscl2dov sdo data output valid after sck edge pic16 f 87/88 pic16 lf 87/88 ? ? ? ? 50 145 ns ns 81* tdov2sch, tdov2scl sdo data output setup to sck edge t cy ?? ns 82* tssl2dov sdo data output valid after ss edge ? ? 50 ns 83* tsch2ssh, tscl2ssh ss after sck edge 1.5 t cy + 40 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note : refer to figure 18-3 for load conditions. 91 92 93 scl sda start condition stop condition 90
? 2003 microchip technology inc. preliminary ds30487b-page 185 pic16f87/88 table 18-9: i 2 c bus start/stop bits requirements figure 18-15: i 2 c bus data timing param no. symbol characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ? 91* t hd : sta start condition 100 khz mode 4000 ? ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? ? 92* t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? 93 t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? * these parameters are characterized but not tested. note: refer to figure 18-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16f87/88 ds30487b-page 186 preliminary ? 2003 microchip technology inc. table 18-10: i 2 c bus data requirements param. no. symbol characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 ? s 400 khz mode 0.6 ? s ssp module 1.5 t cy ? 101* t low clock low time 100 khz mode 4.7 ? s 400 khz mode 1.3 ? s ssp module 1.5 t cy ? 102* t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 - 400 pf 103* t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 - 400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91* t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106* t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107* t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92* t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109* t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110* t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s c b bus capacitive loading ? 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
? 2003 microchip technology inc. preliminary ds30487b-page 187 pic16f87/88 figure 18-16: usart synchronous transmission (master/slave) timing table 18-11: usart synchronous transmission requirements figure 18-17: usart synchronous receive (master/slave) timing table 18-12: usart synchronous receive requirements param no. sym characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & slave) clock high to data out valid pic16 f 87/88 ? ? 80 ns pic16 lf 87/88 ? ? 100 ns 121 tckrf clock out rise time and fall time (master mode) pic16 f 87/88 ? ? 45 ns pic16 lf 87/88 ? ? 50 ns 122 tdtrf data out rise time and fall time pic16 f 87/88 ? ? 45 ns pic16 lf 87/88 ? ? 50 ns ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameter s are for design guidance only and are not tested. param no. sym characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & slave) data setup before ck (dt setup time) 15 ? ? ns 126 tckl2dtl data hold after ck (dt hold time) 15 ? ? ns ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 18-3 for load conditions. 121 121 122 rb5/tx/ck rb2/rx/dt pin pin 120 note: refer to figure 18-3 for load conditions. 125 126 rb5/tx/ck rb2/rx/dt pin pin
pic16f87/88 ds30487b-page 188 preliminary ? 2003 microchip technology inc. table 18-13: a/d converter characteristics: pic16f87/88 (industrial, extended) pic16lf87/88 (industrial) param no. sym characteristic min typ? max units conditions a01 n r resolution ? ? 10 bits bit v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error ? ? < 2 lsb v ref = v dd = 5.12v, v ss v ain v ref a07 e gn gain error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 ? monotonicity (3) ? guaranteed ? ? v ss v ain v ref a20 v ref reference voltage 2.5 2.2 ? ? v dd + 0.3 v dd + 0.3 v v -40c to +85c 0c to +85c a21 v ref + reference voltage high av dd ? 2.5v av dd + 0.3v v a22 v ref - reference voltage low av ss ? 0.3v v ref + ? 2.0v v a25 v ain analog input voltage v ss ? 0.3v ? v ref + 0.3v v a30 z ain recommended impedance of analog voltage source ??2.5k ? see (note 4) a50 i ref v ref input current (2) ? ? ? ? 5 500 a a during v ain acquisition. based on differential of v hold to v ain to charge c hold , see section 12.1 ?a/d acquisition requirements? . during a/d conversion cycle. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 2: the a/d conversion result never dec reases with an increase in the i nput voltage, and has no missing codes. 3: the maximum allowed impedance for analog voltage source is 10 k ? . this requires higher acquisition times.
? 2003 microchip technology inc. preliminary ds30487b-page 189 pic16f87/88 figure 18-18: a/d conversion timing table 18-14: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 987 210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy . . . . . . param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period pic16 f 87/88 1.6 ? ? st osc based, v ref 3.0v pic16 lf 87/88 3.0 ? ? st osc based, v ref 2.0v pic16 f 87/88 2.0 4.0 6.0 s a/d rc mode pic16 lf 87/88 3.0 6.0 9.0 s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) ?12t ad 132 t acq acquisition time (note 2) 10* 40 ? ? ? s s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 12.1 ?a/d acquisition requirements? for minimum conditions.
pic16f87/88 ds30487b-page 190 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 191 pic16f87/88 19.0 dc and ac characteristics graphs and tables no graphs and tables are available at this time.
pic16f87/88 ds30487b-page 192 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 193 pic16f87/88 20.0 packaging information 20.1 package marking information 18-lead pdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example pic16f87/88-i/p 0310017 yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx 18-lead soic xxxxxxxxxxxx 0310017 04/so example pic16f87/88- yywwnnn xxxxxxxxxxx xxxxxxxxxxx 20-lead ssop 0310017 20/ss pic16f87- example legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. 28-lead qfn example xxxxxxxx xxxxxxxx yywwnnn pic16f87 -i/ml 0310017
pic16f87/88 ds30487b-page 194 preliminary ? 2003 microchip technology inc. 18-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 22.99 22.80 22.61 .905 .898 .890 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb e p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-007 significant characteristic
? 2003 microchip technology inc. preliminary ds30487b-page 195 pic16f87/88 18-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.30 0.27 0.23 .012 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 11.73 11.53 11.33 .462 .454 .446 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units l c h 45 1 2 d p n b e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-051 significant characteristic
pic16f87/88 ds30487b-page 196 preliminary ? 2003 microchip technology inc. 20-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072 significant characteristic
? 2003 microchip technology inc. preliminary ds30487b-page 197 pic16f87/88 28-lead plastic quad flat no lead package (ml) 6x6 mm body, punch singulated (qfn) lead width *controlling parameter drawing no. c04-114 notes: mold draft angle top dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" (0.254mm) per side. b .009 12 .011 .014 0.23 12 0.28 0.35 pitch number of pins overall width standoff molded package length overall length molded package width molded package thickness overall height max units dimension limits a2 a1 e1 d d1 e n p a .026 .236 bsc .000 .226 bsc inches .026 bsc min 28 nom max 0.65 .031 .002 0.00 6.00 bsc 5.75 bsc millimeters* .039 min 28 0.65 bsc nom 0.80 0.05 1.00 .008 ref base thickness a3 0.20 ref jedec equivalent: mmo-220 0.85 .033 .0004 0.01 .236 bsc .226 bsc 6.00 bsc 5.75 bsc lead length tie bar width l .020 .024 .030 0.50 0.60 0.75 r .005 .007 .010 0.13 0.17 0.23 tie bar length q .012 .016 .026 0.30 0.40 0.65 chamfer ch .009 .017 .024 0.24 0.42 0.60 e2 d2 exposed pad width exposed pad length .140 .146 .152 3.55 3.70 3.85 .140 .146 .152 3.55 3.70 3.85 d e e1 n 1 2 d1 a a2 exposed metal pads bottom view top view q l r p a1 a3 ch x 45 b d2 e2
pic16f87/88 ds30487b-page 198 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 199 pic16f87/88 appendix a: revision history revision a (november 2003) original data sheet for pic16f87/88 devices. revision b (august 2003) the specifications in section 18.0 ?electrical characteristics? have been updated to include the addition of maximum specifications to the dc characteristics tables, text clarification has been made to section 4.6.2 ?clock switching? , and there have been minor updates to the data sheet text. appendix b: device differences the differences between the devices in this data sheet are listed in table b-1. table b-1: differences between the pic16f87 and pic16f88 features pic16f87 pic16f88 analog-to-digital converter n/a 10-bit, 7-channel
pic16f87/88 ds30487b-page 200 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 201 pic16f87/88 index a a/d acquisition requirements ........................................ 117 adif bit .................................................................... 116 analog-to-digital converter ...................................... 113 associated registers ............................................... 120 calculating acquisition time .................................... 117 configuring analog port pins ................................... 118 configuring the interrupt .......................................... 116 configuring the module ............................................ 116 conversion clock ..................................................... 118 conversions ............................................................. 119 converter characteristics ........................................ 188 delays ...................................................................... 117 effects of a reset .................................................. 120 go/done bit ........................................................... 116 internal sampling switch (rss) impedance ............. 117 operation during sleep ......................................... 120 result registers ....................................................... 119 source impedance ................................................... 117 time delays ............................................................. 117 using the ccp trigger ............................................. 120 absolute maximum ratings ............................................. 163 ack .................................................................................... 93 adcon0 register ...................................................... 14 , 113 adcon1 register ...................................................... 15 , 113 addressable universal synchronous asynchronous receiver transmitter. see usart. adresh register ...................................................... 14 , 113 adresh, adresl register pair .................................... 116 adresl register ...................................................... 15 , 113 ansel register ..............................................15 , 52 , 58 , 113 application notes an556 (implementing a table read) ........................ 25 an578 (use of the ssp module in the i 2 c multi-master environment) ........................... 87 an607 (power-up trouble shooting) ....................... 133 assembler mpasm assembler .................................................. 157 asynchronous reception associated registers ....................................... 105 , 107 asynchronous transmission associated registers ............................................... 103 b baud rate generator associated registers ................................................. 99 bf bit ................................................................................. 92 block diagrams a/d ........................................................................... 116 analog input model .......................................... 117 , 125 capture mode operation ........................................... 82 comparator i/o operating modes ............................ 122 comparator output .................................................. 124 comparator voltage reference ............................... 128 compare mode operation ......................................... 83 fail-safe clock monitor ............................................ 144 in-circuit serial programming connection ............... 147 interrupt logic .......................................................... 139 on-chip reset circuit .............................................. 132 pic16f87 ..................................................................... 6 pic16f88 ..................................................................... 7 pwm .......................................................................... 84 ra0/an0:ra1/an1 pins ............................................ 52 ra2/an2/cv ref /v ref - pin ....................................... 53 ra3/an3/v ref +/c1out pin ..................................... 53 ra4/t0cki/c2out pin ............................................. 54 ra5/mclr /v pp pin ................................................... 54 ra6/osc2/clko pin ................................................ 55 ra7/osc1/clki pin .................................................. 56 rb0 pin ..................................................................... 59 rb1 pin ..................................................................... 60 rb2 pin ..................................................................... 61 rb3 pin ..................................................................... 62 rb4 pin ..................................................................... 63 rb5 pin ..................................................................... 64 rb6 pin ..................................................................... 65 rb7 pin ..................................................................... 66 recommended mclr circuit .................................. 133 ssp in i 2 c mode ........................................................ 92 ssp in spi mode ....................................................... 90 system clock ............................................................. 41 timer0/wdt prescaler .............................................. 67 timer1 ....................................................................... 73 timer2 ....................................................................... 79 usart receive ................................................104 , 106 usart transmit ...................................................... 102 watchdog timer (wdt) ........................................... 141 bor. see brown-out reset. brgh bit ............................................................................ 99 brown-out reset (bor) ............................ 129 , 132 , 133 , 135 bor status (bor bit) ............................................... 24 c c compilers mplab c17 ............................................................. 158 mplab c18 ............................................................. 158 mplab c30 ............................................................. 158 capture/compare/pwm (ccp) ......................................... 81 capture mode ............................................................ 82 capture, compare and timer1 associated registers ......................................... 83 ccp pin configuration ............................................... 83 ccp prescaler ........................................................... 82 ccp timer resources ............................................... 81 ccp1if ...................................................................... 82 ccpr1 ...................................................................... 82 ccpr1h:ccpr1l ..................................................... 82 compare mode .......................................................... 83 special event trigger ........................................ 83 special trigger output of ccp1 ........................ 83 pwm and timer2 associated registers .................... 85 pwm mode ................................................................ 84 pwm, example frequencies/resolutions ................. 85 software interrupt mode ............................................ 83 timer1 mode selection .............................................. 83 ccp1con register ........................................................... 14 ccp1m0 bit ....................................................................... 81 ccp1m1 bit ....................................................................... 81 ccp1m2 bit ....................................................................... 81 ccp1m3 bit ....................................................................... 81 ccp1x bit .......................................................................... 81 ccp1y bit .......................................................................... 81 ccpr1h register .........................................................14 , 81
pic16f87/88 ds30487b-page 202 ? 2003 microchip technology inc. ccpr1l register ......................................................... 14 , 81 clock sources .................................................................... 39 selection using osccon register ........................... 39 clock switching .................................................................. 39 transition and the watchdog timer ........................... 40 cmcon register ............................................................... 15 code examples call of a subroutine in page 1 from page 0 ............... 25 changing between capture prescalers ..................... 82 changing prescaler assignment from wdt to timer0 ................................................... 69 erasing a flash program memory row .................. 31 implementing a real-time clock using a timer1 interrupt service .................................... 77 indirect addressing .................................................... 26 initializing porta ...................................................... 51 reading a 16-bit free-running timer ........................ 74 reading data eeprom ............................................. 29 reading flash program memory ............................ 30 saving status, w and pclath registers ........... 140 writing a 16-bit free-running timer .......................... 74 writing to data eeprom ........................................... 29 writing to flash program memory ........................... 33 code protection ....................................................... 129 , 147 comparator module ......................................................... 121 analog input connection considerations ................. 125 associated registers ............................................... 126 configuration ............................................................ 122 effects of a reset .................................................. 125 interrupts .................................................................. 124 operation ................................................................. 123 operation during sleep ......................................... 125 outputs ..................................................................... 123 reference ................................................................. 123 response time ........................................................ 123 comparator specifications ............................................... 175 comparator voltage reference ....................................... 127 associated registers ............................................... 128 computed goto ............................................................... 25 configuration bits ............................................................. 129 crystal and ceramic resonators ....................................... 35 cvrcon register ............................................................. 15 d data eeprom memory ..................................................... 27 associated registers ................................................. 34 eeadr register ........................................................ 27 eeadrh register ...................................................... 27 eecon1 register ...................................................... 27 eecon2 register ...................................................... 27 eedata register ...................................................... 27 eedath register ...................................................... 27 operation during code protect .................................. 34 protection against spurious writes ............................ 34 reading ...................................................................... 29 write complete flag (eeif bit) .................................. 27 writing ........................................................................ 29 data memory special function registers ........................................ 14 dc and ac characteristics graphs and tables ................................................... 191 dc characteristics internal rc accuracy ............................................... 172 pic16f87/88, pic16lf87/88 ................................... 173 power-down and supply current ............................. 166 supply voltage ......................................................... 165 demonstration boards picdem 1 ................................................................ 160 picdem 17 .............................................................. 160 picdem 18r pic18c601/801 ................................. 161 picdem 2 plus ........................................................ 160 picdem 3 pic16c92x ............................................ 160 picdem 4 ................................................................ 160 picdem lin pic16c43x ........................................ 161 picdem usb pic16c7x5 ...................................... 161 picdem.net internet/ethernet ................................. 160 development support ...................................................... 157 device differences ........................................................... 199 device overview .................................................................. 5 direct addressing ............................................................... 26 e eeadr register ...........................................................16 , 27 eeadrh register .........................................................16 , 27 eecon1 register .........................................................16 , 27 eecon2 register .........................................................16 , 27 eedata register .........................................................16 , 27 eedath register .........................................................16 , 27 electrical characteristics .................................................. 163 endurance ........................................................................... 1 errata ................................................................................... 4 evaluation and programming tools ................................. 161 exiting sleep with an interrupt ......................................... 50 external clock input ........................................................... 36 external clock input (ra4/t0cki). see timer0. external interrupt input (rb0/int). see interrupt sources. external reference signal ............................................... 123 f fail-safe clock monitor .............................................129 , 144 flash program memory ................................................... 27 associated registers ................................................. 34 eeadr register ........................................................ 27 eeadrh register ..................................................... 27 eecon1 register ...................................................... 27 eecon2 register ...................................................... 27 eedata register ...................................................... 27 eedath register ...................................................... 27 erasing ....................................................................... 30 reading ..................................................................... 30 writing ........................................................................ 32 fsr register ..........................................................14 , 15 , 26 i i/o ports ............................................................................. 51 porta ...................................................................... 51 portb ...................................................................... 57 trisb register .......................................................... 57 i 2 c addressing ................................................................. 93 associated registers ................................................. 95 master mode .............................................................. 95 mode .......................................................................... 92 mode selection .......................................................... 92 multi-master mode ..................................................... 95 reception ................................................................... 93 scl and sda pins ..................................................... 92 slave mode ................................................................ 92 transmission ............................................................. 93 id locations ..............................................................129 , 147 in-circuit debugger .......................................................... 147 in-circuit serial programming .......................................... 129
? 2003 microchip technology inc. preliminary ds30487b-page 203 pic16f87/88 in-circuit serial programming (icsp) .............................. 147 indf register .........................................................14 , 15 , 26 indirect addressing ............................................................ 26 instruction set .................................................................. 149 addlw .................................................................... 151 addwf .................................................................... 151 andlw .................................................................... 151 andwf .................................................................... 151 bcf .......................................................................... 151 bsf .......................................................................... 151 btfsc ..................................................................... 152 btfss ..................................................................... 152 call ........................................................................ 152 clrf ........................................................................ 152 clrw ...................................................................... 152 clrwdt .................................................................. 152 comf ...................................................................... 153 decf ....................................................................... 153 decfsz ................................................................... 153 descriptions ............................................................. 151 format ...................................................................... 149 goto ...................................................................... 153 incf ......................................................................... 153 incfsz .................................................................... 153 iorlw ..................................................................... 154 iorwf ..................................................................... 154 movf ....................................................................... 154 movlw ................................................................... 154 movwf ................................................................... 154 nop ......................................................................... 154 read-modify-write operations ................................ 149 retfie .................................................................... 155 retlw .................................................................... 155 return .................................................................. 155 rlf .......................................................................... 155 rrf .......................................................................... 155 sleep ..................................................................... 155 sublw .................................................................... 156 subwf .................................................................... 156 summary table ........................................................ 150 swapf .................................................................... 156 xorlw .................................................................... 156 xorwf .................................................................... 156 int interrupt (rb0/int). see interrupt sources. intcon register gie bit ........................................................................ 19 inte bit ...................................................................... 19 intf bit ...................................................................... 19 peie bit ...................................................................... 19 rbie bit ..................................................................... 19 rbif bit ...................................................................... 19 tmr0ie bit ................................................................. 19 internal oscillator block ..................................................... 37 intrc modes ............................................................ 38 internal reference signal ................................................. 123 interrupt sources ...................................................... 129 , 138 rb0/int pin, external .............................................. 140 tmr0 overflow ........................................................ 140 usart receive/transmit complete ......................... 97 interrupts rb7:rb4 port change ............................................... 57 interrupts, context saving during .................................... 140 interrupts, enable bits a/d converter interrupt enable (adie bit) ................ 20 ccp1 interrupt enable (ccp1ie bit) ......................... 20 comparator interrupt enable (cmie bit) .................... 22 eeprom write operation interrupt enable (eeie bit) ........................................................... 22 global interrupt enable (gie bit) ........................19 , 138 interrupt-on-change (rb7:rb4) enable (rbie bit) ......................................................... 140 oscillator fail interrupt enable (osfie bit) ............... 22 peripheral interrupt enable (peie bit) ....................... 19 port change interrupt enable (rbie bit) ................... 19 rb0/int enable (inte bit) ........................................ 19 synchronous serial port (ssp) interrupt enable (sspie bit) ........................................................ 20 tmr0 overflow enable (tmr0ie bit) ........................ 19 tmr1 overflow interrupt enable (tmr1ie bit) ......... 20 tmr2 to pr2 match interrupt enable (tmr2ie bit) ...................................................... 20 usart interrupt enable (rcie bit) ........................... 20 usart transmit interrupt enable (txie bit) ............ 20 interrupts, flag bits a/d converter interrupt flag (adif bit) ..................... 21 ccp1 interrupt flag (ccp1if bit) ............................. 21 comparator interrupt flag (cmif bit) ........................ 23 eeprom write operation interrupt flag (eeif bit) ........................................................... 23 interrupt-on-change (rb7:rb4) flag (rbif bit) ....................................................19 , 140 oscillator fail interrupt flag (osfif bit) ................... 23 rb0/int flag (intf bit) ............................................ 19 synchronous serial port (ssp) interrupt flag (sspif bit) ......................................................... 21 tmr0 overflow flag (tmr0if bit) .......................... 140 tmr1 overflow interrupt flag (tmr1if bit) .............. 21 tmr2 to pr2 interrupt flag (tmr2if bit) ................. 21 usart receive interrupt flag (rcif bit) ................. 21 usart transmit interrupt flag (txif bit) ................. 21 intrc modes adjustment ................................................................. 38 l loading of pc .................................................................... 25 low-voltage icsp programming ..................................... 148 m master clear (mclr ) mclr reset, normal operation .......................132 , 135 mclr reset, sleep ........................................132 , 135 operation and esd protection ................................ 133 memory organization ........................................................ 11 data memory ............................................................. 11 program memory ....................................................... 11 mplab asm30 assembler, linker, librarian .................. 158 mplab icd 2 in-circuit debugger .................................. 159 mplab ice 2000 high performance universal in-circuit emulator ................................................... 159 mplab ice 4000 high performance universal in-circuit emulator ................................................... 159 mplab integrated development environment software ............................................. 157 mplink object linker/mplib object librarian ............... 158
pic16f87/88 ds30487b-page 204 ? 2003 microchip technology inc. o opcode field descriptions ............................................... 149 option register intedg bit ................................................................ 18 ps2:ps0 bits .............................................................. 18 psa bit ....................................................................... 18 rbpu bit .................................................................... 18 t0cs bit ..................................................................... 18 t0se bit ..................................................................... 18 osccon register ............................................................. 15 oscillator configuration ...................................................... 35 ecio .......................................................................... 35 extrc ..................................................................... 134 hs ...................................................................... 35 , 134 intio1 ........................................................................ 35 intio2 ........................................................................ 35 intrc ...................................................................... 134 lp ....................................................................... 35 , 134 rc ........................................................................ 35 , 37 rcio .......................................................................... 35 xt ....................................................................... 35 , 134 oscillator control register modifying ircf bits ................................................... 41 clock transition sequence ................................ 41 oscillator delay upon power-up, wake-up and clock switching .......................................................... 42 oscillator start-up timer (ost) ............................... 129 , 133 oscillator switching ............................................................ 39 osctune register ........................................................... 15 p packaging information ..................................................... 193 marking .................................................................... 193 paging, program memory .................................................. 25 pcl register .......................................................... 14 , 15 , 25 pclath register ................................................... 14 , 15 , 25 pcon register .......................................................... 15 , 134 bor bit ...................................................................... 24 por bit ...................................................................... 24 pickit 1 flash starter kit ............................................... 161 picstart plus development programmer .................... 159 pie1 register ..................................................................... 15 adie bit ...................................................................... 20 ccp1ie bit ................................................................. 20 rcie bit ..................................................................... 20 sspie bit ................................................................... 20 tmr1ie bit ................................................................. 20 tmr2ie bit ................................................................. 20 txie bit ...................................................................... 20 pie2 register ..................................................................... 15 cmie bit ..................................................................... 22 eeie bit ...................................................................... 22 osfie bit ................................................................... 22 pinout descriptions pic16f87/88 ................................................................ 8 pir1 register ..................................................................... 14 adif bit ...................................................................... 21 ccp1if bit ................................................................. 21 rcif bit ...................................................................... 21 sspif bit .................................................................... 21 tmr1if bit ................................................................. 21 tmr2if bit ................................................................. 21 txif bit ...................................................................... 21 pir2 register .................................................................... 14 cmif bit ..................................................................... 23 eeif bit ...................................................................... 23 osfif bit ................................................................... 23 pop ................................................................................... 25 por. see power-on reset. porta ................................................................................ 8 associated register summary .................................. 52 porta register ........................................................ 14 portb ................................................................................ 9 associated register summary .................................. 58 portb register ........................................................ 14 pull-up enable (rbpu bit) ......................................... 18 rb0/int edge select (intedg bit) .......................... 18 rb0/int pin, external .............................................. 140 rb2/sdo/rx/dt pin ............................................98 , 99 rb5/ss /tx/ck pin .................................................... 98 rb7:rb4 interrupt-on-change ................................ 140 rb7:rb4 interrupt-on-change enable (rbie bit) ......................................................... 140 rb7:rb4 interrupt-on-change flag (rbif bit) ....................................................19 , 140 trisb register .....................................................16 , 97 portb register ................................................................ 16 postscaler, wdt assignment (psa bit) ................................................ 18 rate select (ps2:ps0 bits) ....................................... 18 power managed modes ..................................................... 43 rc_run .................................................................... 43 sec_run .................................................................. 44 sec_run/rc_run to primary clock source .......... 45 power-down mode. see sleep. power-on reset (por) ............................. 129 , 132 , 133 , 135 por status (por bit) ............................................... 24 power control (pcon) register .............................. 134 power-down (pd bit) ............................................... 132 time-out (to bit) ................................................17 , 132 power-up timer (pwrt) ..........................................129 , 133 pr2 register ................................................................15 , 79 prescaler, timer0 assignment (psa bit) ................................................ 18 rate select (ps2:ps0 bits) ....................................... 18 pro mate ii universal device programmer .................. 159 program counter reset conditions ................................................... 135 program memory interrupt vector .......................................................... 11 map and stack pic16f87/88 ..................................................... 11 paging ........................................................................ 25 reset vector ........................................................... 11 program verification ........................................................ 147 push ................................................................................. 25 r r/w bit ............................................................................... 93 ra0/an0 pin ........................................................................ 8 ra1/an1 pin ........................................................................ 8 ra2/an2/cv ref /v ref - pin .................................................. 8 ra3/an3/v ref +/c1out pin ............................................... 8 ra4/an4/t0cki/c2out pin ............................................... 8 ra5/mclr /v pp pin ............................................................. 8 ra6/osc2/clko pin .......................................................... 8 ra7/osc1/clki pin ............................................................ 8
? 2003 microchip technology inc. preliminary ds30487b-page 205 pic16f87/88 rb0/int/ccp1 pin ............................................................... 9 rb1/sdi/sda pin ................................................................. 9 rb2/sdo/rx/dt pin ........................................................... 9 rb3/pgm/ccp1 pin ............................................................ 9 rb4/sck/scl pin ................................................................ 9 rb5/ss /tx/ck pin ............................................................... 9 rb6/an5/pgc/t1oso/t1cki pin ....................................... 9 rb7/an6/pgd/t1osi pin .................................................... 9 rbif bit .............................................................................. 57 rcio oscillator .................................................................. 37 rcreg register ................................................................ 14 rcsta register ................................................................. 14 adden bit ................................................................. 98 cren bit .................................................................... 98 ferr bit .................................................................... 98 rx9 bit ....................................................................... 98 rx9d bit .................................................................... 98 spen bit .............................................................. 97 , 98 sren bit .................................................................... 98 receive overflow indicator bit, sspov ............................. 89 register file ....................................................................... 12 register file map pic16f87 ................................................................... 12 pic16f88 ................................................................... 13 registers adcon0 (a/d control 0) ......................................... 114 adcon1 (a/d control 1) ......................................... 115 ansel (analog select) ............................................ 113 ccp1con (capture/compare/pwm control 1) ........................................................... 81 cmcon (comparator control) ................................ 121 config1 (configuration word 1) ............................ 130 config2 (configuration word 2) ............................ 131 cvrcon (comparator voltage reference control) ........................................... 127 eecon1 (data eeprom access control 1) ........................................................... 28 fsr ............................................................................ 26 initialization conditions (table) ......................... 135 ? 136 intcon (interrupt control) ........................................ 19 option ..................................................................... 18 option_reg ........................................................... 68 osccon (oscillator control) .................................... 40 osctune (oscillator tuning) ................................... 38 pcon (power control) .............................................. 24 pie1 (peripheral interrupt enable 1) .......................... 20 pie2 (peripheral interrupt enable 2) .......................... 22 pir1 (peripheral interrupt status 1) ........................... 21 pir2 (peripheral interrupt status 2) ........................... 23 rcsta (receive status and control) ........................ 98 special function, summary ....................................... 14 sspcon (synchronous serial port control) ............................................ 89 sspstat (synchronous serial port status) .............................................. 88 status ..................................................................... 17 t1con (timer1 control) ............................................ 72 t2con (timer2 control) ............................................ 80 txsta (transmit status and control) ....................... 97 wdtcon (watchdog timer control) ....................... 142 reset ......................................................................129 , 132 brown-out reset (bor). see brown-out reset (bor). mclr reset. see mclr . power-on reset (por). see power-on reset (por). reset conditions for all registers ........................ 135 reset conditions for pcon register .................... 135 reset conditions for program counter ................. 135 reset conditions for status register ................ 135 wdt reset. see watchdog timer (wdt). revision history ............................................................... 199 rp0 bit ............................................................................... 11 rp1 bit ............................................................................... 11 s sci. see usart. scl .................................................................................... 92 serial communication interface. see usart. slave mode scl ............................................................................ 92 sda ........................................................................... 92 sleep .............................................................. 129 , 132 , 145 software simulator (mplab sim) ................................... 158 software simulator (mplab sim30) ............................... 158 spbrg register ................................................................ 15 special event trigger ...................................................... 120 special features of the cpu ........................................... 129 special function registers ................................................ 14 special function registers (sfrs) .................................... 14 spi associated registers ................................................. 90 serial clock ................................................................ 87 serial data in ............................................................. 87 serial data out .......................................................... 87 slave select ............................................................... 87 ssp ack ........................................................................... 92 i 2 c i 2 c operation ..................................................... 92 sspadd register .............................................................. 15 sspbuf register .............................................................. 14 sspcon register ............................................................. 14 sspov .............................................................................. 89 sspov bit ......................................................................... 92 sspstat register ............................................................ 15 stack .................................................................................. 25 overflows ................................................................... 25 underflow .................................................................. 25 status register c bit ........................................................................... 17 dc bit ........................................................................ 17 irp bit ....................................................................... 17 pd bit .................................................................17 , 132 rp bit ........................................................................ 17 to bit .................................................................17 , 132 z bit ........................................................................... 17 synchronous master reception associated registers ............................................... 110 synchronous master transmission associated registers ............................................... 109 synchronous serial port (ssp) ......................................... 87 overview .................................................................... 87 spi mode ................................................................... 87 synchronous slave reception associated registers ............................................... 112 synchronous slave transmission associated registers ............................................... 111
p ic 16f87/88 ds30487b-page 206 ? 2003 microchip technology inc. t t1ckps0 bit ...................................................................... 72 t1ckps1 bit ...................................................................... 72 t1con register ................................................................. 14 t1oscen bit ..................................................................... 72 t1sync bit ........................................................................ 72 t2ckps0 bit ...................................................................... 80 t2ckps1 bit ...................................................................... 80 t2con register ................................................................. 14 t ad ................................................................................... 118 time-out sequence .......................................................... 134 timer0 ................................................................................ 67 associated registers ................................................. 69 clock source edge select (t0se bit) ........................ 18 clock source select (t0cs bit) ................................. 18 external clock ............................................................ 68 interrupt ...................................................................... 67 operation ................................................................... 67 overflow enable (tmr0ie bit) ................................... 19 overflow flag (tmr0if bit) ..................................... 140 overflow interrupt ..................................................... 140 prescaler .................................................................... 68 t0cki ......................................................................... 68 timer1 ................................................................................ 71 associated registers ................................................. 77 asynchronous counter mode ..................................... 74 reading and writing .......................................... 74 capacitor selection .................................................... 75 counter operation ...................................................... 73 operation ................................................................... 71 operation in timer mode ........................................... 73 oscillator .................................................................... 75 oscillator layout considerations ............................... 75 prescaler .................................................................... 76 resetting timer1 register pair .................................. 76 resetting timer1 using a ccp trigger output .......... 75 synchronized counter mode ...................................... 73 use as a real-time clock ......................................... 76 timer2 ................................................................................ 79 associated registers ................................................. 80 output ........................................................................ 79 postscaler .................................................................. 79 prescaler .................................................................... 79 prescaler and postscaler ........................................... 79 timing diagrams a/d conversion ........................................................ 189 asynchronous master transmission ........................ 103 asynchronous master transmission (back to back) .................................................. 103 asynchronous reception ......................................... 104 asynchronous reception with address byte first ............................................ 107 asynchronous reception with address detect ........ 107 brown-out reset ...................................................... 179 capture/compare/pwm (ccp1) .............................. 181 clko and i/o ........................................................... 178 external clock .......................................................... 177 fail-safe clock monitor ............................................ 144 i 2 c bus data ............................................................ 185 i 2 c bus start/stop bits ...................................... 184 i 2 c reception (7-bit address) .................................... 94 i 2 c transmission (7-bit address) ............................... 94 primary system clock after reset (ec, rc, intrc) ............................................... 48 primary system clock after reset (hs, xt, lp) ..... 47 pwm output .............................................................. 84 reset, watchdog timer, oscillator start-up timer and power-up timer .............................. 179 slow rise time (mclr tied to v dd through rc network) ...................................... 138 spi master mode ....................................................... 91 spi master mode (cke = 0, smp = 0) .................... 182 spi master mode (cke = 1, smp = 1) .................... 182 spi slave mode (cke = 0) .................................91 , 183 spi slave mode (cke = 1) .................................91 , 183 switching to sec_run mode ................................... 44 synchronous reception (master mode, sren) ...... 111 synchronous transmission ..................................... 109 synchronous transmission (through txen) .......... 109 time-out sequence on power-up (mclr tied to v dd through pull-up resistor) .................... 137 time-out sequence on power-up (mclr tied to v dd through rc network): case 1 ............. 137 time-out sequence on power-up (mclr tied to v dd through rc network): case 2 ............. 137 timer0 and timer1 external clock .......................... 180 timer1 incrementing edge ........................................ 73 transition between sec_run/rc_run and primary clock ............................................. 46 two-speed start-up mode ....................................... 143 usart synchronous receive (master/slave) ........ 187 usart synchronous transmission (master/slave) ................................................. 187 wake-up from sleep via interrupt .......................... 146 xt, hs, lp, ec and extrc to rc_run mode ........ 43 timing parameter symbology .......................................... 176 timing requirements a/d conversion ........................................................ 189 capture/compare/pwm (ccp1) ............................. 181 clko and i/o .......................................................... 178 external clock .......................................................... 177 i 2 c bus data ............................................................ 186 i 2 c bus start/stop bits ...................................... 185 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset .............................................. 179 spi mode ................................................................. 184 timer0 and timer1 external clock .......................... 180 usart synchronous receive ................................. 187 usart synchronous transmission ........................ 187 tmr0 register ................................................................... 14 tmr1cs bit ....................................................................... 72 tmr1h register ................................................................ 14 tmr1l register ................................................................. 14 tmr1on bit ....................................................................... 72 tmr2 register ................................................................... 14 tmr2on bit ....................................................................... 80 tmro register .................................................................. 16 toutps0 bit ..................................................................... 80 toutps1 bit ..................................................................... 80 toutps2 bit ..................................................................... 80 toutps3 bit ..................................................................... 80 trisa register .............................................................15 , 51 trisb register .................................................................. 15 two-speed clock start-up mode ..................................... 143 two-speed start-up ......................................................... 129 txreg register ................................................................ 14
? 2003 microchip technology inc. preliminary ds30487b-page 207 pic16f87/88 txsta register ................................................................. 15 brgh bit ................................................................... 97 csrc bit .................................................................... 97 sync bit .................................................................... 97 trmt bit .................................................................... 97 tx9 bit ....................................................................... 97 tx9d bit ..................................................................... 97 txen bit .................................................................... 97 u usart ............................................................................... 97 address detect enable (adden bit) ......................... 98 asynchronous mode ................................................ 102 asynchronous receive (9-bit mode) ........................ 106 asynchronous receive with address detect. see asynchronous receive (9-bit mode). asynchronous receiver ........................................... 104 asynchronous reception ......................................... 105 asynchronous transmitter ....................................... 102 baud rate generator (brg) ...................................... 99 baud rate formula ............................................ 99 baud rates, asynchronous mode (brgh = 0) .............................................. 100 baud rates, asynchronous mode (brgh = 1) .............................................. 100 high baud rate select (brgh bit) .................... 97 intrc baud rates, asynchronous mode (brgh = 0) .............................................. 101 intrc baud rates, asynchronous mode (brgh = 1) .............................................. 101 intrc operation ............................................... 99 low-power mode operation ............................... 99 sampling ............................................................ 99 clock source select (csrc bit) ................................ 97 continuous receive enable (cren bit) .................... 98 framing error (ferr bit) .......................................... 98 mode select (sync bit) ............................................ 97 receive data, 9th bit (rx9d bit) ............................... 98 receive enable, 9-bit (rx9 bit) ................................. 98 serial port enable (spen bit) .............................. 97 , 98 single receive enable (sren bit) ............................ 98 synchronous master mode ...................................... 108 synchronous master reception ............................... 110 synchronous master transmission .......................... 108 synchronous slave mode ........................................ 111 synchronous slave reception ................................. 112 synchronous slave transmit ................................... 111 transmit data, 9th bit (tx9d) .................................... 97 transmit enable (txen bit) ....................................... 97 transmit enable, nine-bit (tx9 bit) ........................... 97 transmit shift register status (trmt bit) ................. 97 usart synchronous receive requirements .................. 187 v v dd pin ................................................................................ 9 voltage reference specifications .................................... 175 v ss pin ................................................................................ 9 w wake-up from sleep ...............................................129 , 146 interrupts ................................................................. 135 mclr reset ............................................................ 135 wdt reset .............................................................. 135 wake-up using interrupts ................................................ 146 watchdog timer (wdt) ............................................129 , 141 associated registers ............................................... 142 wdt reset, normal operation .........................132 , 135 wdt reset, sleep ..........................................132 , 135 wcol ................................................................................ 89 wdtcon register ............................................................ 16 write collision detect bit, wcol ...................................... 89 www, on-line support ...................................................... 4
pic16f87/88 ds30487b-page 208 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30487b-page 209 pic16f87/88 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
pic16f87/88 ds30487b-page 210 preliminary ? 2003 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30487b pic16f87/88 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2003 microchip technology inc. preliminary ds30487b-page 211 pic16f87/88 pic16f87/88 product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. part no. x /xx xxx pattern package temperature range device device pic16f87: standard v dd range pic16f87t: (tape and reel) pic16lf87: extended v dd range temperature range - = 0c to +70c i = -40c to +85c package p = pdip so = soic ss = ssop ml = qfn pattern qtp, sqtp, rom code (factory specified) or special requirements. blank for otp and windowed devices. examples: a) pic16f87-i/p = industrial temp., pdip package, extended v dd limits. b) pic16f87-i/so = industrial temp., soic package, normal v dd limits. note 1: f = cmos flash lf = low-power cmos flash 2: t = in tape and reel - soic, ssop packages only.
ds30487b-page 212 preliminary ? 2003 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 phoenix 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-4338 san jose 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building no. 2 fengxiangnan road, ronggui town shunde city, guangdong 528303, china tel: 86-765-8395507 fax: 86-765-8395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands p. a. de biesbosch 14 nl-5152 sc drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 07/28/03 w orldwide s ales and s ervice

▲Up To Search▲

Price & Availability of PIC16F87-ISO

	To Download PIC16F87-ISO Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .